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參數(shù)資料
| 型號： | CY7C43633 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進先出帶總線匹配) |
| 中文描述： | 512 x36單向同步FIFO瓦特/總線匹配（512 x36單向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 422K |
| 代理商： | CY7C43633 |
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CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
23
PRELIMINARY
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
ploys data lines B
0
–
35
. If the selected Port B bus size is 18 bits,
then the usable width of the Mail2 register employs data lines
B
0
–
17
. (In this case, B
18
–
35
are
“
don
’
t care
”
inputs.) If the se-
lected Port B bus size is 9 bits, then the usable width of the
Mail2 Register employs data lines B
0
8
. (In this case, B
9
35
are
“
don
’
t care
”
inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size,
36 bits of mailbox data are placed on B
0
–
35
. For an 18-bit bus
size, 18 bits of mailbox data are placed on B
0
–
17
. (In this case,
B
18
–
35
are indeterminate.) For a 9-bit bus size, 9 bits of mail-
box data are placed on B
0
–
8
. (In this case, B
9
–
35
are indeter-
minate.)
The Mail2 Register flag (MBF2) is set HIGH by a LOW-to-
HIGH transition on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A
0
–
35
. For an 18-bit bus size, 18 bits of mailbox data are placed
on A
0
–
17
. (In this case, A
18
–
35
are indeterminate.) For a 9-bit
bus size, 9 bits of mailbox data are placed on A
0
–
8
. (In this
case, A
9
–
35
are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be configured in a 36-bit long-word, 18-bit
word, or 9-bit byte format for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Select (BM) determine the Port B bus size. These levels
should be static throughout FIFO operation. Both bus size se-
lections are implemented at the completion of Master Reset,
by the time the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are avail-
able for Port B when the bus size selection is either byte-or
word-size. They are referred to as Big Endian (most significant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH transition of MRS1/MRS2 selects the endian
method that will be active during FIFO operation. BE is a don
’
t
care input when the bus size selected for Port B is long-word.
The endian method is implemented at the completion of Mas-
ter Reset, by the time the Full/Input Ready flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7C436x3. Bus-matching operations
are done after data is read from the FIFO. These bus-matching
operations are not available when transferring data via mailbox
registers. Furthermore, both the word- and byte-size bus se-
lections limit the width of the data bus that can be used for mail
register operations. In this case, only those byte lanes belong-
ing to the selected word- or byte-size bus can carry mailbox
data. The remaining data outputs will be indeterminate. The
remaining data inputs will be don
’
t care inputs. For example,
when a word-size bus is selected, then mailbox data can be
transmitted only between A
0
–
17
and B
0
–
17
. When a byte-size
bus is selected, then mailbox data can be transmitted only be-
tween A
0
–
8
and B
0
–
8
.
Bus-Matching FIFO Reads
Data is read from the FIFO RAM in 36-bit long-word incre-
ments. If a long-word bus size is implemented, the entire long-
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO output regis-
ter, with the rest of the long-word stored in auxiliary registers.
In this case, subsequent FIFO reads output the rest of the
long-word to the FIFO output register.
When reading data from the FIFO in the byte or word format,
the unused B
0
–
35
outputs are indeterminate.
Retransmit (RT)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at least one word has been read since the last reset
cycle. A LOW pulse on RT resets the internal read pointer to
the first physical location of the FIFO. CLKA and CLKB may be
free-running but must be disabled during and t
RTR
after the
retransmit pulse. With every valid read cycle after retransmit,
previously accessed data is read and the read pointer is incre-
mented until it is equal to the write pointer. Flags are governed
by the relative locations of the read and write pointers and are
updated during a retransmit cycle. Data written to the FIFO
after activation of RT are transmitted also. The full depth of the
FIFO can be repeatedly transmitted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43623 | 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進先出帶總線匹配) |
| CY7C43643 | 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進先出帶總線匹配) |
| CY7C43663 | 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進先出帶總線匹配) |
| CY7C43683 | 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進先出帶總線匹配) |
| CY7C43634 | 512 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(512 x36 x2 雙向同步先進先出 帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43642-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP |
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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