參數(shù)資料
型號: CY7C1471V33
廠商: Cypress Semiconductor Corp.
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述: 72兆位(2米x 36/4M x 18/1M × 72)流體系結(jié)構(gòu),通過與總線延遲(帶總線延遲結(jié)構(gòu)的72兆位通過的SRAM(2米x 36/4M x 18/1M × 72)流的SRAM)
文件頁數(shù): 25/32頁
文件大?。?/td> 1138K
代理商: CY7C1471V33
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *J
Page 25 of 32
Figure 2
shows NOP, STALL and DESELECT Cycles waveform.
[20, 21, 23]
Figure 2. NOP, STALL and DESELECT Cycles
Switching Waveforms
(continued)
READ
Q(A3)
4
5
6
7
8
9
10
A3
A4
A5
D(A4)
1
2
3
CLK
CE
WE
CEN
BW
[A:D]
ADV/LD
ADDRESS
DQ
COMMAND
WRITE
D(A4)
STALL
WRITE
D(A1)
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tCHZ
A1
A2
Q(A2)
D(A1)
Q(A3)
tDOH
Q(A5)
Note
23.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
相關(guān)PDF資料
PDF描述
CY7C1482V25-200BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZI 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZXI 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1471V33-100AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk
CY7C1471V33-100AXI 制造商:Cypress Semiconductor 功能描述:
CY7C1471V33-117AXC 功能描述:靜態(tài)隨機存取存儲器 2Mx36 3.3V NoBL FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1471V33-117AXCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk
CY7C1471V33-133AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 6.5NS 100TQFP - Bulk