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參數(shù)資料
| 型號： | CY7C1471V33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM) |
| 中文描述： | 72兆位（2米x 36/4M x 18/1M × 72）流體系結(jié)構(gòu)，通過與總線延遲（帶總線延遲結(jié)構(gòu)的72兆位通過的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM） |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | CY7C1471V33 |
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CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *J
Page 18 of 32
Identification Register Definitions
Instruction Field
CY7C1471V33
(2Mx36)
CY7C1473V33
(4Mx18)
CY7C1475V33
(1Mx72)
Description
Revision Number (31:29)
Device Depth (28:24)
[13]
000
000
000
Describes the version number
01011
01011
01011
Reserved for internal use
Architecture/Memory
Type(23:18)
001001
001001
001001
Defines memory type and architecture
Bus Width/Density(17:12)
100100
010100
110100
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
00000110100
Enables unique identification of SRAM
vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
71
-
Bit Size (x18)
3
1
32
52
-
Bit Size (x72)
3
1
32
-
110
Instruction
Bypass
ID
Boundary Scan Order – 165FBGA
Boundary Scan Order – 209BGA
Identification Codes
Instruction
Code
000
Description
EXTEST
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
Note
13.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
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PDF描述 |
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| CY7C1482V25-200BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V25-200BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V25-200BZI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
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| CY7C1480V25-200BZXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1471V33-100AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk |
| CY7C1471V33-100AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1471V33-117AXC | 功能描述:靜態(tài)隨機存取存儲器 2Mx36 3.3V NoBL FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1471V33-117AXCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk |
| CY7C1471V33-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 6.5NS 100TQFP - Bulk |
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