參數(shù)資料
型號(hào)： CY7C1471V33
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流體系結(jié)構(gòu)，通過(guò)與總線延遲（帶總線延遲結(jié)構(gòu)的72兆位通過(guò)的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM）
文件頁(yè)數(shù)： 23/32頁(yè)
文件大?。?/td> 1138K
代理商： CY7C1471V33
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *J
Page 23 of 32
Switching Characteristics
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when V
DDQ
= 3.3V and
is 1.25V when V
DDQ
= 2.5V. Test conditions shown in (a) of
“AC Test Loads and Waveforms” on page 22
unless otherwise noted.
Parameter
t
POWER [16]
Clock
Description
133 MHz
117 MHz
Unit
Min
Max
Min
Max
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
7.5
10
ns
Clock HIGH
2.5
3.0
ns
Clock LOW
2.5
3.0
ns
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
Data Output Valid After CLK Rise
6.5
8.5
ns
Data Output Hold After CLK Rise
Clock to Low-Z
[17, 18, 19]
Clock to High-Z
[17, 18, 19]
2.5
2.5
ns
3.0
3.0
ns
3.8
4.5
ns
OE LOW to Output Valid
OE LOW to Output Low-Z
[17, 18, 19]
OE HIGH to Output High-Z
[17, 18, 19]
3.0
3.8
ns
0
0
ns
3.0
4.0
ns
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
Address Setup Before CLK Rise
1.5
1.5
ns
ADV/LD Setup Before CLK Rise
1.5
1.5
ns
WE, BW
X
Setup Before CLK Rise
CEN Setup Before CLK Rise
Data Input Setup Before CLK Rise
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
Chip Enable Setup Before CLK Rise
1.5
1.5
ns
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Address Hold After CLK Rise
0.5
0.5
ns
ADV/LD Hold After CLK Rise
0.5
0.5
ns
WE, BW
X
Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
ns
0.5
0.5
ns
Data Input Hold After CLK Rise
0.5
0.5
ns
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes
16.This part has an internal voltage regulator; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially, before a read or write operation
can be initiated.
17.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of
“AC Test Loads and Waveforms” on page 22
. Transition is measured ±200 mV
from steady-state voltage.
18.At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.
19.This parameter is sampled and not 100% tested.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1471V33-100AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk
CY7C1471V33-100AXI 制造商:Cypress Semiconductor 功能描述:
CY7C1471V33-117AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx36 3.3V NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1471V33-117AXCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 8.5NS 100TQFP - Bulk
CY7C1471V33-133AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 6.5NS 100TQFP - Bulk
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