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參數(shù)資料
| 型號： | CY7C1460AV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結構的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM架構的總線延遲（帶總線延遲結構的36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM） |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 465K |
| 代理商： | CY7C1460AV25 |
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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document #: 38-05354 Rev. *D
Page 19 of 27
Switching Characteristics
Over the Operating Range
[21, 22]
Parameter
t
Power[17]
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
Description
–250
–200
–167
Unit
ms
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
V
CC
(typical) to the first access read or write
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
4.0
5.0
6.0
ns
MHz
ns
ns
250
200
167
1.5
1.5
2.0
2.0
2.4
2.4
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
[18, 19, 20]
Clock to Low-Z
[18, 19, 20]
OE HIGH to Output High-Z
[18, 19, 20]
OE LOW to Output Low-Z
[18, 19, 20]
2.6
2.6
3.2
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
1.0
1.5
1.5
2.6
3.0
3.4
1.0
1.3
1.5
2.6
3.0
3.4
0
0
0
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
WE, BW
x
Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
x
Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
17.This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
18.t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20.This parameter is sampled and not 100% tested.
21.Timing reference is 1.25V when V
=
2.5V and 0.9V when V
= 1.8V.
22.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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| CY7C1462AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結構的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1460AV25-167AXC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 2.5V NoBL PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1460AV25-167AXCT | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 2.5V NoBL PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1460AV25-167BZC | 功能描述:靜態(tài)隨機存取存儲器 36MB (1Mx36) 2.5v 167MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1460AV25-167BZCT | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 2.5V NoBL PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1460AV25-167BZI | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 36MBIT 1MX36 3.4NS 165FBGA - Bulk |
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