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參數(shù)資料
| 型號： | CY7C1412AV18-167BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 18 QDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 1021K |
| 代理商： | CY7C1412AV18-167BZXC |
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *D
Page 10 of 25
L
H
–
L-H
During the data portion of a write sequence
:
CY7C1410AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
remains unaltered,
CY7C1412AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
remains unaltered.
During the data portion of a write sequence
:
CY7C1410AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
remains unaltered,
CY7C1412AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
remains unaltered.
During the data portion of a write sequence
:
CY7C1410AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
remains unaltered,
CY7C1412AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
remains unaltered.
No data is written into the devices during this portion of a write operation.
No data is written into the devices during this portion of a write operation.
H
L
L-H
–
H
L
–
L-H
H
H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1414AV18)
[2, 8]
BWS
0
BWS
1
BWS
2
BWS
3
K
K
Comments
L
L
L
L
L-H
–
During the data portion of a write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the data portion of a write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the data portion of a write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
remains unaltered.
During the data portion of a write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
remains unaltered.
During the data portion of a write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
remains unaltered.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
L
L
L
L
–
L-H
L
H
H
H
L-H
–
L
H
H
H
–
L-H
H
L
H
H
L-H
–
H
L
H
H
–
L-H
H
H
L
H
L-H
–
H
H
L
H
–
L-H
H
H
H
L
L-H
H
H
H
L
–
L-H
H
H
H
H
H
H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1425AV18)
BWS
0
K
K
Comments
L
L-H
–
During the data portion of a write sequence
:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
During the data portion of a write sequence
:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L
–
L-H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1410AV18 and CY7C1412AV18) (continued)
[2, 8]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
K
K
Comments
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1412AV18-167BZXI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1412AV18-200BZI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1412AV18-200BZXC | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1412AV18-200BZXI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1412AV18-250BZI | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1412AV18-167BZXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 QDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1412AV18200BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1412AV18-200BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 QDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1412AV18-200BZI | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 QDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1412AV18-200BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 QDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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