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參數(shù)資料
| 型號(hào)： | CY7C1394BV18-200BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 中文描述： | 512K X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 446K |
| 代理商： | CY7C1394BV18-200BZXC |
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CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 22 of 27
t
CQOH
t
CHCQX
Echo Clock Hold after C/C
Clock Rise
Echo Clock High to Data
Change
Echo Clock High to Data
Change
Clock (C/C) Rise to High-Z
(Active to High-Z)
[26, 27]
Clock (C/C) Rise to
Low-Z
[26, 27]
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
t
CQD
t
CQHQV
–
0.27
–
0.27
–
0.30
–
0.35
–
0.40
ns
t
CQDOH
t
CQHQX
–0.27
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
ns
t
CHZ
t
CHQZ
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
CLZ
t
CHQX1
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
DLL Timing
t
KC Var
t
KC lock
t
KC Reset
t
KC Var
t
KC lock
t
KC Reset
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
ns
1024
30
1024
30
1024
30
1024
30
1024
30
Cycles
ns
Notes:
26.t
, t
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
27.At any given voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
Switching Characteristics
Over the Operating Range
[22,23]
(continued)
Cypress
Parameter
Consortium
Parameter
Description
300 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
278 MHz
250 MHz
200 MHz
167 MHz
Unit
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1394BV18-200BZXI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZC | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZXC | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZXI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1399-12VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 12ns 28-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:R ASSET CODE/B REV - Bulk |
| CY7C139912ZC | 制造商:CYP 功能描述:* |
| CY7C1399-12ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1399-15VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 15ns 28-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C139915VI | 制造商:CYPRESS 功能描述:* |
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