參數(shù)資料
型號(hào)： CY7C1394BV18-200BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述： 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù)： 10/27頁
文件大?。?/td> 446K
代理商： CY7C1394BV18-200BZXC
CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 10 of 27
Write Cycle Descriptions
(CY7C1394BV18)
[2, 8]
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written into
the device.
L-H During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written into
the device.
-
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
–
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
–
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
L
L
L
L
–
L
H
H
H
L-H
L
H
H
H
–
H
L
H
H
L-H
H
L
H
H
–
H
H
L
H
L-H
H
H
L
H
–
H
H
H
L
L-H
H
H
H
L
–
H
H
H
H
H
H
H
H
L-H
–
Write Cycle Descriptions
(CY7C1992BV18)
[2, 8]
BWS
0
L
L
H
H
K
K
–
Comments
L-H
–
L-H
–
During the Data portion of a Write sequence, the single byte (D
[8:0]
) is written into the device.
During the Data portion of a Write sequence, the single byte (D
[8:0]
) is written into the device.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L-H
–
L-H
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1394BV18-200BZXI 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-250BZC 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-250BZI 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-250BZXC 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-250BZXI 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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