參數(shù)資料
型號(hào)： CY7C1394BV18-200BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述： 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 14/27頁(yè)
文件大?。?/td> 446K
代理商： CY7C1394BV18-200BZXC
CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 14 of 27
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range
[10, 13, 14]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Test Conditions
I
OH
=
2.0 mA
I
OH
=
100
μ
A
I
OL
= 2.0 mA
I
OL
= 100
μ
A
Min.
1.4
1.6
Max.
Unit
V
V
V
V
V
V
μ
A
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and OutputLoad Current
0.4
0.2
0.65V
DD
–0.3
–5
V
DD
+ 0.3
0.35V
DD
5
GND
≤
V
I
≤
V
DD
TAP AC Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
t
TCYC
t
TF
t
TH
t
TL
Set-up Times
t
TMSS
t
TDIS
Description
Min.
50
Max.
Unit
ns
MHz
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
20
20
20
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
5
5
ns
ns
Notes:
10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
12.Test conditions are specified using the load in TAP AC test conditions. t
/t
= 1 ns.
13.Overshoot: V
(AC) < V
+0.85V (Pulse width less than t
TCYC
/2); Undershoot V
IL
(AC) >
–1.5V (Pulse width less than t
TCYC
/2).
14.All voltage referenced to ground.
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
106
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
[+] Feedback
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