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參數(shù)資料
| 型號： | CY7C1394BV18-200BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 中文描述： | 512K X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 446K |
| 代理商： | CY7C1394BV18-200BZXC |
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CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 16 of 27
Identification Register Definitions
Instruction Field
Revision Number
(31:29)
Cypress Device
ID (28:12)
Cypress JEDEC
ID (11:1)
Value
Description
Version number.
CY7C1392BV18
000
CY7C1992BV18
000
CY7C1393BV18
000
CY7C1394BV18
000
11010100010000101
11010100010001101
11010100010010101 11010100010100101 Defines the type
of SRAM.
Allows unique
identification of
SRAM vendor.
Indicate the
presence of an
ID register.
00000110100
00000110100
00000110100
00000110100
ID Register
Presence (0)
1
1
1
1
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
3
1
32
107
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
Description
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1394BV18-200BZXI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZC | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZXC | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-250BZXI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1399-12VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 12ns 28-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:R ASSET CODE/B REV - Bulk |
| CY7C139912ZC | 制造商:CYP 功能描述:* |
| CY7C1399-12ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1399-15VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 15ns 28-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C139915VI | 制造商:CYPRESS 功能描述:* |
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