參數(shù)資料
型號： CY7C1386D-167BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
中文描述： 512K X 36 CACHE SRAM, 3.4 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)： 20/30頁
文件大?。?/td> 974K
代理商： CY7C1386D-167BZC
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Document Number: 38-05545 Rev. *E
Page 20 of 30
Switching Characteristics
Over the Operating Range
[20, 21]
Parameter
Description
–250
–200
–167
Unit
Min
Max
Min
Max
Min
Max
t
POWER
Clock
V
DD
(Typical) to the First Access
[22]
1
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
4.0
5.0
6.0
ns
Clock HIGH
1.7
2.0
2.2
ns
Clock LOW
1.7
2.0
2.2
ns
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
Data Output Valid after CLK Rise
2.6
3.0
3.4
ns
Data Output Hold after CLK Rise
Clock to Low-Z
[23, 24, 25]
Clock to High-Z
[23, 24, 25]
1.0
1.3
1.3
ns
1.0
1.3
1.3
ns
2.6
3.0
3.4
ns
OE LOW to Output Valid
2.6
3.0
3.4
ns
OE LOW to Output Low-Z
[23, 24, 25]
OE HIGH to Output High-Z
[23, 24, 25]
0
0
0
ns
2.6
3.0
3.4
ns
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
Address Set-up Before CLK Rise
1.2
1.4
1.5
ns
ADSC, ADSP Set-up Before CLK Rise
1.2
1.4
1.5
ns
ADV Set-up Before CLK Rise
1.2
1.4
1.5
ns
GW, BWE, BW
X
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
1.2
1.4
1.5
ns
Chip Enable Set-Up Before CLK Rise
1.2
1.4
1.5
ns
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.5
ns
ADV Hold After CLK Rise
0.3
0.4
0.5
ns
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
0.3
0.4
0.5
ns
Chip Enable Hold After CLK Rise
0.3
0.4
0.5
ns
Notes
20.Timing reference level is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
23.t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
24.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
25.This parameter is sampled and not 100% tested.
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1386D-167BZI Replacement for Intersil part number 8100604EA. Buy from authorized manufacturer Rochester Electronics.
CY7C1386D-167BZXC 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1386D-167BZXI 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
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參數(shù)描述
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CY7C1386D-200AXCT 功能描述:靜態(tài)隨機存取存儲器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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CY7C1386D-250AXC 制造商:Cypress Semiconductor 功能描述:
CY7C1386S-167AXC 功能描述:靜態(tài)隨機存取存儲器 CY7C1386S-167AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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