- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379071 > CY7C1386D-167BZXI (CYPRESS SEMICONDUCTOR CORP) 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM PDF資料下載
參數(shù)資料
| 型號： | CY7C1386D-167BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 3.4 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 974K |
| 代理商： | CY7C1386D-167BZXI |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Cypress Semiconductor Corporation
Document Number: 38-05545 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised Feburary 09, 2007
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
Depth expansion without wait state
3.3V core power supply (V
DD
)
2.5V or 3.3V IO power supply (V
DDQ)
Fast clock-to-output times
— 2.6 ns (for 250 MHz device)
Provides high-performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
CY7C1386D/CY7C1387D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FBGA package. CY7C1386F/CY7C1387F available in
Pb-free and non Pb-free 119-ball BGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
ZZ sleep mode option
Functional Description
[1]
The
SRAM integrates 512K x 36/1M x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE
1
), depth
expansion chip enables (CE
2
and
CE
3 [2]
), burst control inputs
(ADSC, ADSP, and ADV), write enables (BW
X
, and BWE), and
global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see
Pin Configurations on page 3
and
Truth Table
[4, 5, 6, 7, 8]
on page 9
for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
inputs. GW active LOW causes all bytes to be written. This
device incorporates an additional pipelined enable register
which delays turning off the output buffers an additional cycle
when a deselect is executed.This feature allows depth
expansion without penalizing system performance.
The
operates from a +3.3V core power supply while all outputs
operate with a +3.3V or +2.5V supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
Selection Guide
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines
on
www.cypress.com
.
2. CE
3
and CE
2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in Single Chip Enable.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1386D-200AXC | 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM |
| CY7C1386D-200AXI | 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM |
| CY7C1386D-200BZC | 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM |
| CY7C1386D-200BZI | 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM |
| CY7C1386D-200BZXC | 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1386D-200AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1386D-200AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 2CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1386D-200BGCT | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 512KX36 3NS 119BGA - Tape and Reel |
| CY7C1386D-250AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1386S-167AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1386S-167AXC RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。