參數(shù)資料
型號(hào)： CY7C1355C-117BGC
廠商： Cypress Semiconductor Corp.
英文描述： 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
中文描述： 9兆位（256 × 36/512K × 18）流體系結(jié)構(gòu)，通過(guò)與總線延遲靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 23/32頁(yè)
文件大?。?/td> 496K
代理商： CY7C1355C-117BGC
PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 23 of 33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage on V
DD
Relative to GND........–0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ..................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C 3.3V
– 5%/+10% 2.5V – 5%
-40°C to +85°C
V
DD
V
DDQ
to
V
DD
Electrical Characteristics
Over the Operating Range
[17, 18]
Parameter
V
DD
V
DDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
2.0
Max.
3.6
V
DD
2.625
Unit
V
V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V, V
DD
= Min., I
OH
= –4.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OH
= –1.0 mA
V
DDQ
= 3.3V, V
DD
= Min., I
OL
= 8.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OL
= 1.0 mA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
GND
≤
V
I
≤
V
DDQ
V
OH
Output HIGH Voltage
V
V
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
V
OL
Output LOW Voltage
0.4
0.4
V
IH
Input HIGH Voltage
[17]
2.0
1.7
–0.3
–0.3
–5
–30
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
V
IL
Input LOW Voltage
[17]
I
X
Input Load
Input Current of MODE Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
5
Input Current of ZZ
–5
30
5
250
220
180
40
I
OZ
I
DD
Output Leakage Current GND
≤
V
I
≤
V
DD,
Output Disabled
V
DD
Operating Supply
Current
f = f
MAX
= 1/t
CYC
–5
V
DD
= Max., I
OUT
= 0 mA,
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All speeds
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
f = f
MAX
, inputs switching
V
DD
= Max, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DD
– 0.3V,
f = 0, inputs static
V
DD
= Max, Device Deselected, or
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
, inputs switching
V
DD
= Max, Device Deselected,
V
IN
≥
V
DD
- 0.3V or V
IN
≤
0.3V
, f =
0, inputs static
mA
I
SB2
All speeds
30
mA
I
SB3
All speeds
40
mA
I
SB4
All Speeds
40
mA
Notes:
17.Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC) > –2V (Pulse width less than t
CYC
/2).
18.T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
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