參數(shù)資料
型號(hào)： CY7C1355C-117BGC
廠商： Cypress Semiconductor Corp.
英文描述： 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
中文描述： 9兆位（256 × 36/512K × 18）流體系結(jié)構(gòu)，通過與總線延遲靜態(tài)存儲(chǔ)器
文件頁數(shù)： 11/32頁
文件大?。?/td> 496K
代理商： CY7C1355C-117BGC
PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 11 of 33
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
1
H
CE
2
CE
3
X
ZZ
L
ADV/LD
L
WE
X
BW
X
X
OE
X
CEN
L
CLK
DQ
Deselect Cycle
None
X
L->H Three-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H Three-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H Three-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H Three-State
READ Cycle
(Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
READ Cycle
(Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
NOP/DUMMY READ
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H Three-State
DUMMY READ
(Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H Three-State
WRITE Cycle
(Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
WRITE Cycle
(Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/WRITE ABORT
(Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H Three-State
WRITE ABORT
(Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H Three-State
IGNORE CLOCK
EDGE (Stall)
Current
X
X
X
L
X
X
X
X
H
L->H
-
SLEEP MODE
None
X
X
X
H
X
X
X
X
X
X
Three-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BW
, and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQs and DQP
X
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP
X
= Three-state when
OE is inactive or when the device is deselected, and DQs and DQP
X
= data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
X
is valid. Appropriate write will be done based on which byte write is active.
相關(guān)PDF資料
PDF描述
CY7C1355C-117BGI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-117BZC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-117BZI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133AC 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C-133AI 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1355C-133AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1355C-133AXCKJ 制造商:Cypress Semiconductor 功能描述:
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CY7C1355C-133AXI 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1355C-133AXIT 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
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