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參數(shù)資料
| 型號(hào)： | CY7C1355C-117BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 9兆位（256 × 36/512K × 18）流體系結(jié)構(gòu)，通過與總線延遲靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 16/32頁(yè) |
| 文件大?。?/td> | 496K |
| 代理商： | CY7C1355C-117BGC |
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PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 16 of 33
TAP Timing
3.3V TAP AC Test Conditions
Input pulse levels........ ........................................V
SS
to 3.3V
Input rise and fall times..................... ..............................1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
TAP AC Switching Characteristics
Over the operating Range
[10, 11]
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
Output Times
t
TDOV
t
TDOX
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
10.t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC Test Conditions. t
R
/t
F
= 1 ns.
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
ns
20
25
25
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
5
ns
ns
0
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
5
5
5
ns
ns
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
TDO
1.5V
20pF
Z = 50
50
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1355C-117BGI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355C-117BZC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355C-117BZI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355C-133AC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
| CY7C1355C-133AI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1355C-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1355C-133AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1355C-133AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V NoBL Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1355C-133AXI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1355C-133AXIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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