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參數(shù)資料
| 型號(hào)： | CY7C1325F-117AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 4-Mb (256K x 18) Flow-Through Sync SRAM |
| 中文描述： | 256K X 18 CACHE SRAM, 7.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大小： | 430K |
| 代理商： | CY7C1325F-117AC |
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4-Mb (256K x 18) Flow-Through Sync SRAM
CY7C1325F
Cypress Semiconductor Corporation
Document #: 38-05215 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 13, 2004
Features
256K X 18 common I/O
3.3V –5% and +10% core power supply (V
DD
)
2.5V or 3.3V I/O supply (V
DDQ
)
Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.0 ns (100-MHz version)
— 11.0ns (66-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Offered in JEDEC-standard 100-pin TQFP and 119-ball
BGA packages
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1325F is a 262,144 x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1325F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1325F operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Logic Block Diagram
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
CE
1
CE
2
CE
3
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
GW
BWE
A0,A1,A
BW
B
BW
A
DQ
B
,DQP
B
WRITE REGISTER
DQ
A
,DQP
A
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
DQs
DQP
A
DQP
B
DQ
B
,DQP
B
WRITE DRIVER
DQ
A
,DQP
A
WRITE DRIVER
SLEEP
CONTROL
ZZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1325 | 256K x 18 Synchronous 3.3V Cache RAM(3.3V 256K x 18 同步高速緩沖存儲(chǔ)器 RAM) |
| CY7C1327G | 4-Mbit (256K x 18) Pipelined Sync SRAM(4-Mb (256K x 18)管道式同步SRAM) |
| CY7C1327 | 256K x 18 Synchronous-Pipelined Cache RAM( 256K x 18 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| CY7C132 | 2Kx8 Dual-Port Static RAM(2K x 8 雙端口靜態(tài) RAM) |
| CY7C142 | 2Kx8 Dual-Port Static RAM(2K x 8 雙端口靜態(tài) RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1325F-133ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1325G-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1325G-100AXCB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1325G-100AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1325G-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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