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參數(shù)資料
| 型號(hào)： | CY7C1327 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache RAM( 256K x 18 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| 中文描述： | 256 × 18同步流水線緩存內(nèi)存（256 × 18同步流水線式高速緩沖存儲(chǔ)器的RAM） |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | CY7C1327 |
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256K x 18 Synchronous-Pipelined Cache RAM
CY7C1327
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 6, 1999
Features
Supports 100-MHz bus for Pentium
and PowerPC
operations with zero wait states
Fully registered inputs and outputs for pipelined
operation
256K by 18 common I/O architecture
3.3V core power supply
2.5V / 3.3V I/O operation
Fast clock-to-output times
—3.5 ns (for 166-MHz device)
—4.0 ns (for 133-MHz device)
—5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1327 is a 3.3V, 256K by 18 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
The CY7C1327 I/O pins can operate at either the 2.5V or the
3.3V level. The I/O pins are 3.3V tolerant when V
DDQ
=2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1327 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW
[1:0]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
ADSP
A
[17:0]
GW
BWE
BW
1
BW
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
ROUTPUT
CLK
INPUT
REGISTERS
CLK
256KX18
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CLR
SLEEP
18
18
18
16
16
18
(A
[1;0]
)
2
MODE
Logic Block Diagram
DQ
[15:0]
DP
[1:0]
DQ[15:8], DP[1]
BYTEWRITE
DQ[7:0], DP[0]
BYTEWRITE
REGISTERS
D
Q
D
Q
ENABLE CE
REGISTER
D
CE
Q
ENABLE DELAY
REGISTER
D
Q
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1327 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1327-166ACQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1327A-133AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1327A-133ACT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY7C1327B-100BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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