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參數(shù)資料
| 型號： | CY7C1330 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 32 Synchronous-Pipelined Cache RAM(64K x 32 同步流水線式高速緩沖存儲器 RAM) |
| 中文描述： | 64K的× 32同步流水線緩存內(nèi)存（64K的× 32同步流水線式高速緩沖存儲器的RAM） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 317K |
| 代理商： | CY7C1330 |
PRELIMINARY
64K x 32 Synchronous-Pipelined Cache RAM
Functional Description
CY7C1330
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 15, 1997
Features
Low (1.65 mW) standby power (f=0, L version)
Supports 117-MHz bus operations with zero wait states
Fully registered inputs and outputs for pipelined oper-
ation
64K x 32 common I/O architecture
3.3V V
DD
and 2.5V V
DDQ
for 2.5V I/Os
Fast Clock-to-output times
—5.0 ns (for 117-MHz device)
—5.5 ns (for 100-MHz device)
—8.5 ns (for 66-MHz device)
User-selectable burst counter supporting interleaved
or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option
Supports Stop Clock option for power conservation
The CY7C1330 is 3.3V 64K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 5 ns (117-MHz ver-
sion). A 2-bit on-chip wraparound burst counter captures the
first address in a burst sequence and automatically increments
the address for the rest of the burst access.
The CY7C1330 supports either the interleaved burst se-
quence or a linear burst sequence used by processors such
as the PowerPC. The burst sequence is selected through the
MODE pin. Accesses can be initiated by asserting either the
processor address strobe (ADSP) or the controller address
strobe (ADSC) at clock rise. Address advancement through
the burst sequence is controlled by the ADV input.
Byte write operations are qualified with the four Byte Write
Select (BW
[0-3]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous chip selects (CE
1
, CE
2
, CE
3
) and an asyn-
chronous output enable (OE) provide for easy bank selection
and output three-state control. In order to provide proper data
during depth expansion, OE is masked during the first clock of
a read cycle when going from a deselected to a selected state.
CLK
ADV
ADSC
ADSP
GW
BWE
BW
3
BW
2
BW
1
BW
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
DQ[31:24]
ADDRESS
REGISTER
D
Q
ROUTPUT
CLK
INPUT
REGISTERS
CLK
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CLR
SLEEP
DQ[23:16]
D
Q
D
Q
DQ[15:8]
BDQ[7:0]
D
Q
ENABLE
REGISTER
CLK
D
CE
Q
ENREGISTER
CLK
D
Q
32
32
16
14
14
16
(A
0
,A
1
)
2
MODE
Logic Block Diagram
A
[15:0]
DQ
[31:0]
64KX32
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1350G | 4-Mbit (128K x 36) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1350G_06 | 4-Mbit (128K x 36) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1350G-100BGXC | 4-Mbit (128K x 36) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1350G-100BGXI | 4-Mbit (128K x 36) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1350G-133BGXC | 4-Mbit (128K x 36) Pipelined SRAM with NoBL⑩ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C133-25JC | 制造商:Cypress Semiconductor 功能描述:Static RAM, 2Kx16, 68 Pin, Plastic, LDCC |
| CY7C1332AV25-200BGC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1333-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C133-35JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 35ns 68-Pin PLCC |
| CY7C1333-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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