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參數(shù)資料
| 型號(hào)： | CY7C1325 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous 3.3V Cache RAM(3.3V 256K x 18 同步高速緩沖存儲(chǔ)器 RAM) |
| 中文描述： | 256 × 18同步3.3高速緩存內(nèi)存（3.3 256 × 18同步高速緩沖存儲(chǔ)器的RAM） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 264K |
| 代理商： | CY7C1325 |
256K x 18 Synchronous
3.3V Cache RAM
Functional Description
CY7C1325
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 9, 1999
Features
Supports 117-MHz microprocessor cache systems with
zero wait states
256K by 18 common I/O
Fast clock-to-output times
—7.5 ns (117-MHz version)
Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
Separate processor and controller address strobes pro-
vides direct interface with the processor and external
cache controller
Synchronous self-timed write
Asynchronous output enable
I/Os capable of 2.5–3.3V operation
JEDEC-standard pinout
100-pin TQFP packaging
ZZ “sleep” mode
The CY7C1325 is a 3.3V, 256K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1325 allows both an interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the Cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
CLK
ADV
ADSC
ADSP
A
[17:0]
GW
BWE
BW
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
INPUT
REGISTERS
CLK
256K X 18
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CE
CLR
SLEEP
D
Q
DQ[15:8]
BDQ[7:0]
D
Q
ENABLE
REGISTER
CLK
D
CE
Q
18
18
18
16
16
18
(A
0
,A
1
)
2
MODE
Logic Block Diagram
DQ
[15:0]
DP
[1:0]
BW
1
Selection Guide
7C1325–117
7C1325–100
7C1325–80
7C1325–50
Maximum Access Time (ns)
7.5
8.0
8.5
11.0
Maximum Operating Current (mA)
350
325
300
250
Maximum Standby Current (mA)
2.0
2.0
2.0
2.0
Intel and Pentium are registered trademarks of Intel Corporation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1325-100AC | 制造商:Cypress Semiconductor 功能描述:256K X 18 CACHE SRAM, 8 ns, PQFP100 |
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| CY7C1325A-100AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1325A-117AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1325B100AC | 制造商:Cypress Semiconductor 功能描述: |
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