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參數(shù)資料
| 型號(hào)： | CY7C1324 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 128K x 18 Synchronous Cache RAM(3.3V 128K x 18 同步高速緩沖存儲(chǔ)器 RAM) |
| 中文描述： | 3.3 128K的× 18同步高速緩存內(nèi)存（3.3 128K的× 18同步高速緩沖存儲(chǔ)器的RAM） |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大小： | 265K |
| 代理商： | CY7C1324 |
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3.3V 128K x 18 Synchronous
Cache RAM
CY7C1324
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 4, 1999
Features
Supports 117-MHz microprocessor cache systems with
zero wait states
128K by 18 common I/O
Fast clock-to-output times
—7.5 ns (117 MHz)
Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
Separate processor and controller address strobes pro-
vides direct interface with the processor and external
cache controller
Synchronous self-timed write
Asynchronous output enable
I/Os capable of 2.5–3.3V operation
JEDEC-standard pinout
100-pin TQFP packaging
ZZ “sleep” mode
Functional Description
The CY7C1324 is a 3.3V, 128K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1324 allows both interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH input on
MODE selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be initiat-
ed with the Processor Address Strobe (ADSP) or the cache
Controller Address Strobe (ADSC) inputs. Address advance-
ment is controlled by the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Pin
Selection Guide
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BW
0
CE
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
INPUT
REGISTERS
CLK
128K X 18
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CE
CLR
SLEEP
D
Q
DQ[15:8]
BDQ[7:0]
D
Q
ENABLE
REGISTER
CLK
D
CE
Q
18
18
17
15
15
17
(A
0
,A
1
)
2
MODE
Logic Block Diagram
DQ
[15:0]
DP
[1:0]
BW
1
7C1324–117
7.5
350
1.0
7C1324–100
8.0
325
1.0
7C1324–80
8.5
300
1.0
7C1324–50
11.0
250
1.0
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1325F | 4-Mb (256K x 18) Flow-Through Sync SRAM |
| CY7C1325F-117AC | 4-Mb (256K x 18) Flow-Through Sync SRAM |
| CY7C1325 | 256K x 18 Synchronous 3.3V Cache RAM(3.3V 256K x 18 同步高速緩沖存儲(chǔ)器 RAM) |
| CY7C1327G | 4-Mbit (256K x 18) Pipelined Sync SRAM(4-Mb (256K x 18)管道式同步SRAM) |
| CY7C1327 | 256K x 18 Synchronous-Pipelined Cache RAM( 256K x 18 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1324-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1324A-117AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1324F-117ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1324F-117AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1324F-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 2.25MBIT 128KX18 6.5NS 100TQFP - Bulk |
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