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參數(shù)資料
| 型號： | CY7C0837AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| 中文描述： | FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙口RAM（FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙端口RAM）的 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 775K |
| 代理商： | CY7C0837AV |
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Document #: 38-06059 Rev. *Q
Page 14 of 28
t
SD
t
HD
t
SAD
t
HAD
t
SCN
t
HCN
t
SRST
t
HRST
t
SCM
t
HCM
t
OE
t
OLZ[27,28]
t
OHZ[27,28]
t
CD2
t
CA2
t
CM2
Input Data Set-up Time
2.3
2.5
2.5
3.0
ns
Input Data Hold Time
0.6
0.6
0.6
0.6
ns
ADS Set-up Time
2.3
2.5
NA
NA
ns
ADS Hold Time
0.6
0.6
NA
NA
ns
CNTEN Set-up Time
2.3
2.5
NA
NA
ns
CNTEN Hold Time
0.6
0.6
NA
NA
ns
CNTRST Set-up Time
2.3
2.5
NA
NA
ns
CNTRST Hold Time
0.6
0.6
NA
NA
ns
CNT/MSK Set-up Time
2.3
2.5
NA
NA
ns
CNT/MSK Hold Time
0.6
0.6
NA
NA
ns
Output Enable to Data Valid
4.0
4.4
4.7
5.0
ns
OE to Low Z
0
0
ns
OE to High Z
0
4.0
0
4.4
4.7
5.0
ns
Clock to Data Valid
4.0
4.4
4.7
5.0
ns
Clock to Counter Address Valid
4.0
4.4
NA
NA
ns
Clock to Mask Register Readback
Valid
4.0
4.4
NA
NA
ns
t
DC
t
CKHZ[27,28]
t
CKLZ[27, 28]
t
SINT
t
RINT
t
SCINT
t
RCINT
Port to Port Delays
Data Output Hold After Clock HIGH
1.0
1.0
1.0
1.0
ns
Clock HIGH to Output High Z
0
4.0
0
4.4
4.7
5.0
ns
Clock HIGH to Output Low Z
1.0
4.0
1.0
4.4
1.0
4.7
1.0
5.0
ns
Clock to INT Set Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10
ns
Clock to INT Reset Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10
ns
Clock to CNTINT Set Time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
Clock to CNTINT Reset time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
t
CCS
Master Reset Timing
Clock to Clock Skew
5.2
6.0
6.0
8.0
ns
t
RS
t
RS
t
RSR
t
RSF
t
RSCNTINT
Master Reset Pulse Width
7.0
7.5
7.5
10
ns
Master Reset Set-up Time
6.0
6.0
6.0
8.5
ns
Master Reset Recovery Time
6.0
7.5
7.5
10
ns
Master Reset to Outputs Inactive
10.0
10.0
10.0
10.0
ns
Master Reset to Counter Interrupt
Flag Reset Time
10.0
10.0
NA
NA
ns
Notes:
27.This parameter is guaranteed by design, but it is not production tested.
28.Test conditions used are Load 2.
Switching Characteristics
Over the Operating Range
(continued)
Parameter
Description
-167
-133
-100
Unit
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0833AV
CY7C0833AV
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C0851V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K x 36同步雙端口RAM) |
| CY7C0852V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-133AC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-133AI | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0837AV-167BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 512K-Bit 32K x 18 4ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0850AV-133AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C0850AV-133AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0850AV-133BBC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C0850AV-133BBI | 制造商:Cypress Semiconductor 功能描述: |
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