參數(shù)資料
型號: CY62148EV30
廠商: Cypress Semiconductor Corp.
英文描述: 4-Mbit (512K x 8) Static RAM
中文描述: 4兆位(為512k × 8)靜態(tài)RAM
文件頁數(shù): 3/12頁
文件大?。?/td> 919K
代理商: CY62148EV30
CY62148EV30 MoBL
Document #: 38-05576 Rev. *F
Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Supply Voltage to Ground
Potential......................................... –0.3V to V
CC(max)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
........................–0.3V to V
CC(max)
+ 0.3V
Electrical Characteristics
(Over the Operating Range)
DC Input Voltage
[5, 6]
.....................–0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Product
Range
Ambient
Temperature
V
CC
[7]
CY62148EV30 Industrial –40°C to +85°C
2.2V to 3.6V
Parameter
Description
Test Conditions
45 ns
Typ
[4]
55 ns
[1]
Unit
Min
Max
Min Typ
[4]
Max
V
OH
Output HIGH
Voltage
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70V
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V For VFBGA and
2.0
2.0
V
2.4
2.4
V
V
OL
Output LOW
Voltage
0.4
0.2
V
0.4
0.4
V
V
IH
Input HIGH
Voltage
1.8
V
CC
+ 0.3V 1.8
V
CC
+ 0.3V 2.2
0.6
V
CC
+ 0.3V
V
CC
+ 0.3V
V
2.2
V
V
IL
Input LOW
Voltage
TSOP II package
–0.3
V
For SOIC package
–0.3
0.4
[8]
V
V
CC
= 2.7V to 3.6V For VFBGA and
TSOP II package
–0.3
0.8
V
For SOIC package
–0.3
0.6
[8]
I
IX
Input Leakage
Current
GND < V
I
< V
CC
–1
+1
–1
+1
μ
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
, Output Disabled
–1
+1
–1
+1
μ
A
I
CC
V
CC
Operating
Supply Current
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max),
I
OUT
= 0 mA,
CMOS levels
15
20
15
20
mA
2
2.5
2
2.5
I
SB1
Automatic CE
Power Down
Current — CMOS
Inputs
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V
f = f
max
(Address and Data Only),
f = 0 (OE and WE), V
CC
= 3.60V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
1
7
1
7
μ
A
I
SB2 [9]
Automatic CE
Power Down
Current — CMOS
Inputs
1
7
1
7
μ
A
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
= V
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100
μ
s ramp time from 0 to V
and 200
μ
s wait time after V
stabilization.
8. Under DC conditions the device meets a V
of 0.8V (for V
range of 2.7V to 3.6V) and 0.6V (for V
range of 2.2V to 2.7V). However, in dynamic conditions
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to
AN13470 for details.
9. Only chip enable (CE) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
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