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參數(shù)資料
| 型號： | CY62148EV30LL-45ZSXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (512K x 8) Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 45 ns, PDSO32 |
| 封裝： | LEAD FREE, TSOP2-32 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 919K |
| 代理商： | CY62148EV30LL-45ZSXI |
4-Mbit (512K x 8) Static RAM
CY62148EV30 MoBL
Cypress Semiconductor Corporation
Document #: 38-05576 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 18, 2007
Features
Very high speed: 45 ns
— Wide voltage range: 2.20V – 3.60V
Pin compatible with CY62148DV30
Ultra low standby power
— Typical standby current: 1
μ
A
— Maximum standby current: 7
μ
A (Industrial)
Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
Easy memory expansion with CE, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and
32-pin SOIC
[1]
packages
Functional Description
[2]
The CY62148EV30 is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The eight input and output pins (IO
0
through IO
7
) are placed in a high impedance state when the
device is deselected (CE HIGH), the outputs are disabled (OE
HIGH), or during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO
0
through IO
7
)
is then written into the location specified on the address pins
(A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
Notes
1. SOIC package is available only in 55 ns speed bin.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at
http://www.cypress.com
.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
S
POWER
DOWN
CE
WE
OE
A
A
A
A
A
R
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A
[+] Feedback
相關(guān)PDF資料 |
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|---|---|
| CY62148EV30LL-55SXI | 4-Mbit (512K x 8) Static RAM |
| CY62148E | 4-Mbit (512K x 8) Static RAM |
| CY62148ELL | 4-Mbit (512K x 8) Static RAM |
| CY62148ELL-45ZSXI | 4-Mbit (512K x 8) Static RAM |
| CY62148ELL-55SXA | 4-Mbit (512K x 8) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62148EV30LL-45ZSXIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 4M MoBL Ultra LO Pwr HI SPD Micropwr IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62148EV30LL-55SXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 4M MoBL Ultra Lo PWR HI SPD MicroPWR RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62148EV30LL-55SXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 4MBIT SOIC-32 |
| CY62148EV30LL55SXIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 4M-Bit 512K x 8 55ns 32-Pin SOIC T/R |
| CY62148EV30LL-55SXIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 4M MoBL Ultra Lo PWR HI SPD MicroPWR RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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