參數(shù)資料
型號: CY62147EV18LL-55BVXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 55 ns, PBGA48
封裝: 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
文件頁數(shù): 6/12頁
文件大小: 388K
代理商: CY62147EV18LL-55BVXI
CY62147EV18 MoBL2
Document #: 38-05441 Rev. *F
Page 6 of 12
Switching Waveforms
Figure 4
shows the Read Cycle No.1 that is address transition controlled.
[16, 17]
Figure 4. Read Cycle No. 1
Figure 5
shows the Read Cycle No.2 that is OE controlled
.
[17, 18]
Figure 5. Read Cycle No. 2
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH MPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes:
16.The device is continuously selected. OE, CE
= V
IL
, BHE, BLE or both = V
IL
.
17.WE is HIGH for read cycle.
18.Address valid before or similar to CE and BHE, BLE transition LOW.
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