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參數(shù)資料
| 型號： | CY62147EV18LL-55BVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 388K |
| 代理商： | CY62147EV18LL-55BVXI |
Cypress Semiconductor Corporation
Document #: 38-05441 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 01, 2007
CY62147EV18 MoBL2
4-Mbit (256K x 16) Static RAM
Features
■
Very high speed: 55 ns
■
Wide voltage range: 1.65V–2.25V
■
Pin compatible with CY62147DV18
■
Ultra low standby power
Typical standby current: 1
μ
A
Maximum standby current: 7
μ
A
■
Ultra low active power
Typical active current: 2 mA @ f = 1 MHz
■
Ultra low standby power
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in a Pb-free 48-Ball VFBGA package
Functional Description
The CY62147EV18 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO
0
through IO
15
) are placed
in a high impedance state when:
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
When a write operation is active (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the
“Truth Table”
on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines
.
Logic Block Diagram
256K x 16
RAM Array
IO
0
–IO
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
IO
8
–IO
15
CE
WE
BHE
A
1
A
0
A
9
A
10
A
1
BHE
BLE
CE
POWER DOWN
CIRCUIT
相關PDF資料 |
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|---|---|
| CY62147EV30 | 4-Mbit (256K x 16) Static RAM |
| CY62147EV30LL-45BVI | 4-Mbit (256K x 16) Static RAM |
| CY62147EV30LL-45BVXA | 4-Mbit (256K x 16) Static RAM |
| CY62147EV30LL-45BVXI | 4-Mbit (256K x 16) Static RAM |
| CY62147EV30LL-45ZSXI | 4-Mbit (256K x 16) Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62147EV18LL-55BVXIT | 功能描述:靜態(tài)隨機存取存儲器 4M MoBL Ultra Lo PWR HI SPD MicroPWR RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62147EV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62147EV30_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62147EV30_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM Wide voltage range: 2.20 V to 3.60 V |
| CY62147EV30_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256Kx16) Satic RAM |
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