參數(shù)資料
型號: CY62147EV30LL-45BVXA
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 45 ns, PBGA48
封裝: 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
文件頁數(shù): 1/12頁
文件大?。?/td> 517K
代理商: CY62147EV30LL-45BVXA
4-Mbit (256K x 16) Static RAM
CY62147EV30 MoBL
Cypress Semiconductor Corporation
Document #: 38-05440 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 6, 2007
Features
Very high speed: 45 ns
Temperature ranges
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
Wide voltage range: 2.20V–3.60V
Pin compatible with CY62147DV30
Ultra low standby power
— Typical standby current: 1
μ
A
— Maximum standby current: 7
μ
A (Industrial)
Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII
packages
Byte power down feature
Functional Description
[1]
The CY62147EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
Logic Block Diagram
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE HIGH
or both BLE and BHE are HIGH). The input and output pins
(IO
0
through IO
15
) are placed in a high impedance state when:
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through
IO
15
) is written into the location specified on the address pins
(A
0
through A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the
“Truth Table” on page 9
for a
complete description of read and write modes.
256K x 16
RAM Array
IO
0
–IO
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
IO
8
–IO
15
CE
WE
BHE
A
1
A
0
A
9
A
10
A
1
BHE
BLE
CE
POWER DOWN
CIRCUIT
Note
1. For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.
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