參數(shù)資料
型號(hào): CY62147EV18LL-55BVXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 55 ns, PBGA48
封裝: 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
文件頁數(shù): 4/12頁
文件大?。?/td> 388K
代理商: CY62147EV18LL-55BVXI
CY62147EV18 MoBL2
Document #: 38-05441 Rev. *F
Page 4 of 12
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
VFBGA
Package
75
Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
°
C/W
Θ
JC
10
°
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
Parameters
R1
R2
R
TH
V
TH
1.80V
13500
10800
6000
0.80
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
[1]
Max
Unit
V
DR
I
CCDR[7]
V
CC
for Data Retention
Data Retention Current
1.0
V
μ
A
V
CC
= 1.0V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
0.5
5
t
CDR[8]
t
R[9]
Chip Deselect to Data Retention Time
0
ns
Operation Recovery Time
t
RC
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
[10]
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
V
ALL INPUT PULSES
R
TH
R1
Equivalent to: THEVENIN EQUIVALENT
V
CC(min)
t
R
V
CC(min)
t
CDR
V
DR
> 1.0V
DATA RETENTION MODE
V
CC
CE
or
BHE
.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
μ
s or stable at V
CC(min)
> 100
μ
s.
10.BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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