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參數(shù)資料
| 型號(hào)： | CY62146E |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 4兆位（256K × 16）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 449K |
| 代理商： | CY62146E |
CY62146E MoBL
Document #: 001-07970 Rev. *C
Page 5 of 11
Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
Description
45 ns (Ind’l/Auto-A)
Unit
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[15]
Read Cycle Time
45
ns
Address to Data Valid
45
ns
Data Hold from Address Change
10
ns
CE LOW to Data Valid
45
ns
OE LOW to Data Valid
22
ns
OE LOW to Low-Z
[13]
OE HIGH to High-Z
[13, 14]
CE LOW to Low-Z
[13]
CE HIGH to High-Z
[13, 14]
5
ns
18
ns
10
ns
18
ns
CE LOW to Power Up
0
ns
CE HIGH to Power Down
45
ns
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low
[13]
BLE/BHE HIGH to High-Z
[13, 14]
22
ns
5
ns
18
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
45
ns
CE LOW to Write End
Address Setup to Write End
35
ns
35
ns
Address Hold from Write End
0
ns
Address Setup to Write Start
0
ns
WE Pulse Width
35
ns
BLE/BHE LOW to Write End
Data Setup to Write End
35
ns
25
ns
Data Hold from Write End
0
ns
WE LOW to High-Z
[13, 14]
WE HIGH to Low-Z
[13]
18
ns
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 3 ns (1V/ns) or less, timing reference levels of 1.5V, input
pulse levels of 0 to 3V, and output loading of the specified I
/I
as shown in the
“AC Test Loads and Waveforms” on page 4
.
12.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
application note AN13842
for further clarification.
13.At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
14.t
, t
, t
, and t
transitions are measured when the output enters a high impedence state.
15.The internal memory write time is defined by the overlap of WE, CE
= V
, BHE, BLE or both = V
. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[+] Feedback
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| CY62146E_08 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
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