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參數(shù)資料
| 型號： | CY62146E |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 4兆位（256K × 16）靜態(tài)RAM |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 449K |
| 代理商： | CY62146E |
4-Mbit (256K x 16) Static RAM
CY62146E MoBL
Cypress Semiconductor Corporation
Document #: 001-07970 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 4, 2007
Features
Very high speed: 45 ns
Wide voltage range: 4.5V–5.5V
Ultra low standby power
— Typical standby current: 1
μ
A
— Maximum standby current: 7
μ
A
Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 44-pin TSOP II package
Functional Description
[1]
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH). The input and
output pins (IO
0
through IO
15
) are placed in a high impedance
state when:
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
Both byte high enable and byte low enable are disabled
(BHE, BLE HIGH)
When the write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through
IO
15
) is written into the location specified on the address pins
(A
0
through A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
0
to IO
7
.
If Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See the
“Truth Table” on page 9
for a
complete description of read and write modes.
Logic Block Diagram
256K x 16
RAM Array
IO
0
–IO
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
IO
8
–IO
15
CE
WE
BHE
A
1
A
0
A
9
A
10
A
1
Note
1. For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62146E_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62146E_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62146E_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62146E_1106 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM Automatic power down when deselected |
| CY62146E_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256 K x 16) Static RAM |
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