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參數(shù)資料
| 型號(hào)： | CY62146E |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 4兆位（256K × 16）靜態(tài)RAM |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CY62146E |
CY62146E MoBL
Document #: 001-07970 Rev. *C
Page 3 of 11
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. User guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential ............................... –0.5V to + 6V (V
CCmax
+ 0.5V)
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
....................–0.5V to 6V (V
CCmax
+ 0.5V)
DC Input Voltage
[4, 5]
............... –0.5V to 6V (V
CC max
+ 0.5V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage .......................................... >2001V
(MIL-STD-883, Method 3015)
Latch up Current......................................................>200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
[6]
CY62146ELL
Ind’l/Auto-A
–40°C to +85°C 4.5V to 5.5V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A)
Typ
[3]
Unit
Min
Max
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Output HIGH Voltage
I
OH
= –1.0 mA
I
OL
= 2.1 mA
V
CC
= 4.5V to 5.5V
V
CC
= 4.5V to 5.5V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
2.4
V
Output LOW Voltage
0.4
V
Input HIGH Voltage
2.2
V
CC
+ 0.3
0.8
V
Input LOW Voltage
–0.5
V
Input Leakage Current
–1
+1
μ
A
Output Leakage Current
–1
+1
μ
A
V
CC
Operating Supply Current f = f
max
= 1/t
RC
V
CC
= V
CC(max)
f = 1 MHz
I
OUT
= 0 mA
CMOS levels
15
20
mA
2
2.5
I
SB2[7]
Automatic CE Power Down
Current – CMOS Inputs
CE > V
CC
– 0.2V
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CC(max)
1
7
μ
A
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Test Conditions
Max
10
10
Unit
pF
pF
Input Capacitance
Output Capacitance
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
TSOP II
Package
77
Unit
Θ
JA
Thermal Resistance
(junction to ambient)
Thermal Resistance
(junction to case)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
°
C/W
Θ
JC
13
°
C/W
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
5. V
= V
+ 0.75V for pulse durations less than 20 ns.
6. Full device AC operations are based on a minimum of 100
μ
s ramp time from 0 to V
(min) and 200
μ
s wait time after V
stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
[+] Feedback
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