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參數(shù)資料
| 型號(hào)： | CY62146E |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 4兆位（256K × 16）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 449K |
| 代理商： | CY62146E |
CY62146E MoBL
Document #: 001-07970 Rev. *C
Page 4 of 11
AC Test Loads and Waveforms
Figure 1. AC Test Load and Waveforms
Parameters
R1
R2
R
TH
V
TH
5.0V
1800
990
639
1.77
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
[3]
Max
Unit
V
DR
I
CCDR [7]
V
CC
for Data Retention
2
V
Data Retention Current
V
CC
= 2V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Ind’l/Auto-A
1
7
μ
A
t
CDR [8]
Chip Deselect to Data
Retention Time
0
ns
t
R [9]
Operation Recovery Time
t
RC
ns
Data Retention Waveform
[10]
Figure 2. Data Retention Waveform
3V
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
RISE TIME= 1 V/ns
FALL TIME= 1 V/ns
OUTPUT
V
ALL INPUT PULSES
R
TH
R1
EQUIVALENT TO: THEVENIN EQUIVALENT
V
CC(min)
t
R
V
CC(min)
t
CDR
V
DR
> 2.0V
DATA RETENTION MODE
V
CC
CE or
BHE.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V
ramp from V
to V
> 100
μ
s or stable at V
> 100
μ
s.
10.BHE. BLE is the AND of BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling BHE and BLE.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62146E_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62146E_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62146E_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62146E_1106 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM Automatic power down when deselected |
| CY62146E_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256 K x 16) Static RAM |
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