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參數(shù)資料
| 型號(hào)： | CY62137FV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mbit (128K x 16) Static RAM(2Mbit (128K x 16)靜態(tài)RAM) |
| 中文描述： | 2兆位（128K的× 16）靜態(tài)隨機(jī)存儲(chǔ)器（2Mbit的（128K的× 16），靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 449K |
| 代理商： | CY62137FV18 |
CY62137FV18 MoBL
Document #: 001-08030 Rev. *E
Page 5 of 11
Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
Description
55 ns
Unit
Min
Max
Read Cycle
t
RC
Read Cycle Time
55
ns
t
AA
Address to Data Valid
55
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE LOW to Data Valid
55
ns
t
DOE
OE LOW to Data Valid
25
ns
t
LZOE
OE LOW to Low Z
[13]
5
ns
t
HZOE
OE HIGH to High Z
[13, 14]
18
ns
t
LZCE
CE LOW to Low Z
[13]
10
ns
t
HZCE
CE HIGH to High Z
[13, 14]
18
ns
t
PU
CE LOW to power up
0
ns
t
PD
CE HIGH to power down
55
ns
t
DBE
BLE/BHE LOW to data valid
55
ns
t
LZBE
BLE/BHE LOW to Low Z
[13]
10
ns
t
HZBE
Write Cycle
[15]
BLE/BHE HIGH to High Z
[13, 14]
18
ns
t
WC
Write Cycle Time
45
ns
t
SCE
CE LOW to Write End
35
ns
t
AW
Address Setup to Write End
35
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Setup to Write Start
0
ns
t
PWE
WE Pulse Width
35
ns
t
BW
BLE/BHE LOW to Write End
35
ns
t
SD
Data Setup to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[13, 14]
18
ns
t
LZWE
WE HIGH to Low Z
[13]
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
, and output loading of the specified I
/I
as shown in the
“AC Test Loads and Waveforms”
on page 4.
12.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
13.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
14.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
15.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62137FV18_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137FV18_10 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137FV18_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128 K x 16) Static RAM Automatic power down when deselected |
| CY62137FV18LL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137FV18LL-55BVXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 3.0V SUPER LO PWR 128KX16 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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