參數(shù)資料
型號： CY62137FV18
廠商： Cypress Semiconductor Corp.
英文描述： 2-Mbit (128K x 16) Static RAM(2Mbit (128K x 16)靜態(tài)RAM)
中文描述： 2兆位（128K的× 16）靜態(tài)隨機(jī)存儲器（2Mbit的（128K的× 16），靜態(tài)內(nèi)存）
文件頁數(shù)： 1/11頁
文件大?。?/td> 449K
代理商： CY62137FV18
Cypress Semiconductor Corporation
Document #: 001-08030 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 01, 2007
CY62137FV18 MoBL
2-Mbit (128K x 16) Static RAM
Features
■
Very high speed: 55 ns
■
Wide voltage range: 1.65V–2.25V
■
Pin compatible with CY62137CV18
■
Ultra low standby power
Typical standby current: 1
μ
A
Maximum standby current: 5
μ
A
■
Ultra low active power
Typical active current: 1.6 mA @ f = 1 MHz
■
Ultra low standby power
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Byte power down feature
■
Available in a Pb-free 48-Ball VFBGA package
Functional Description
The CY62137FV18 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO
0
through IO
15
) are placed
in a high impedance state when:
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both the Byte High Enable and the Byte Low Enable are
disabled (BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
16
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
16
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from the memory
appears on IO
8
to IO
15
. See the
“Truth Table”
on page 9 for a
complete description of read and write modes.
application note
AN1064, SRAM System Guidelines
.
Logic Block Diagram
128K x 16
RAM Array
IO
0
–IO
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
IO
8
–IO
15
CE
WE
BHE
A
1
A
0
A
9
A
10
BHE
BLE
CE
POWER DOWN
CIRCUIT
相關(guān)PDF資料
PDF描述
CY62137FV30 2-Mbit (128K x 16) Static RAM(2Mbit (128K x 16)靜態(tài)RAM)
CY62137V MoBL 128K x 16 Static RAM(128K x 16 靜態(tài)RAM)
CY62137V18 128K x 16 Static RAM(128K x 16靜態(tài)RAM)
CY62137V 2-Mbit (128K x 16) Static RAM
CY62137VLL-55ZI 2-Mbit (128K x 16) Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY62137FV18_09 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM
CY62137FV18_10 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM
CY62137FV18_11 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128 K x 16) Static RAM Automatic power down when deselected
CY62137FV18LL 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM
CY62137FV18LL-55BVXI 功能描述:靜態(tài)隨機(jī)存取存儲器 SLO 3.0V SUPER LO PWR 128KX16 靜態(tài)隨機(jī)存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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