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參數(shù)資料
| 型號(hào)： | CY62137V18 |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x 16 Static RAM(128K x 16靜態(tài)RAM) |
| 中文描述： | 128K的× 16靜態(tài)RAM（128K的× 16靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | CY62137V18 |
128K x 16 Static RAM
CY62137V MoBL
CY62137V18 MoBL2
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 20, 2000
Features
Low voltage range:
—CY62137V18: 1.65V–1.95V
—CY62137V: 2.7V-3.6V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62137V and CY62137V18 are high-performance
CMOS static RAMs organized as 131,072 words by 16 bits.
This device features advanced circuit design to provide ul-
tra-low active current. This is ideal for providing More Battery
Life (MoBL) in portable applications such as cellular tele-
phones. The device also has an automatic power-down fea-
ture that reduces power consumption by 99% when addresses
are not toggling. The device can also be put into standby mode
when deselected (CE HIGH) or when CE is LOW and both BLE
and BHE are HIGH. The input/output pins (I/O
0
through I/O
15
)
are placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62137V and CY62137V18 are available in 48-ball
FBGA and standard 44-pin TSOP Type II (forward pinout)
packaging.
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Logic Block Diagram
Pin Configurations
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
4
I/O
5
NC
A
4
A
3
A
2
A
1
A
0
OE
BHE
BLE
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
A
5
A
6
A
7
I/O
15
I/O
14
I/O
13
I/O
12
CE
I/O
0
I/O
1
I/O
2
I/O
3
NC
A
8
A
9
A
10
A
11
18
19
20
21
27
26
25
24
22
23
I/O
6
I/O
7
62137V–2
TSOP II (Forward)
128K x 16
RAM Array
I/O
0
–I/O
7
R
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
8
–I/O
15
OE
WE
A
1
62137V–1
A
1
Power Down
Circuit
BHE
BLE
CE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62137V | 2-Mbit (128K x 16) Static RAM |
| CY62137VLL-55ZI | 2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70ZE | 2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70ZI | 2-Mbit (128K x 16) Static RAM |
| CY62137VSL-55ZI | 2-Mbit (128K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62137V18LL-70BAI | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x16 SRAM |
| CY62137VLL-55BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 2M-Bit 128K x 16 55ns 48-Pin FBGA |
| CY62137VLL-55ZI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137VLL-55ZXI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70BAI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述:Static RAM, 128Kx16, 48 Pin, Plastic, BGA |
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