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參數(shù)資料
| 型號： | CY62137V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x 16 Static RAM(128K x 16靜態(tài)RAM) |
| 中文描述： | 128K的× 16靜態(tài)RAM（128K的× 16靜態(tài)RAM）的 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 225K |
| 代理商： | CY62137V18 |
CY62137V MoBL
CY62137V18 MoBL2
5
Switching Characteristics
Over the Operating Range
[4]
70 ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[7, 8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
t
BW
Shaded areas contain preliminary information.
Read Cycle Time
70
ns
Address to Data Valid
70
ns
Data Hold from Address Change
10
ns
CE LOW to Data Valid
70
ns
OE LOW to Data Valid
OE LOW to Low Z
[5]
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[5]
CE HIGH to High Z
[5, 6]
35
ns
5
ns
25
ns
10
ns
25
ns
CE LOW to Power-Up
0
ns
CE HIGH to Power-Down
70
ns
BHE / BLE LOW to Data Valid
70
ns
BHE / BLE LOW to Low Z
10
ns
BHE / BLE HIGH to High Z
25
ns
Write Cycle Time
70
ns
CE LOW to Write End
60
ns
Address Set-Up to Write End
60
ns
Address Hold from Write End
0
ns
Address Set-Up to Write Start
0
ns
WE Pulse Width
50
ns
Data Set-Up to Write End
30
ns
Data Hold from Write End
WE LOW to High Z
[5, 6]
WE HIGH to Low Z
[5]
0
ns
50
ns
10
ns
BHE / BLE LOW to End of Write
60
ns
Notes:
5.
6.
7.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD.
8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62137V | 2-Mbit (128K x 16) Static RAM |
| CY62137VLL-55ZI | 2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70ZE | 2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70ZI | 2-Mbit (128K x 16) Static RAM |
| CY62137VSL-55ZI | 2-Mbit (128K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62137V18LL-70BAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62137VLL-55BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 2M-Bit 128K x 16 55ns 48-Pin FBGA |
| CY62137VLL-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137VLL-55ZXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128K x 16) Static RAM |
| CY62137VLL-70BAI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述:Static RAM, 128Kx16, 48 Pin, Plastic, BGA |
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