參數(shù)資料
型號(hào): CY3950V484-125BBC
廠商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁數(shù): 80/86頁
文件大小: 1212K
代理商: CY3950V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 81 of 86
M26
NC
N1
GND
N2
GND
N3
GND
N4
IO0
N5
IO0
N6[19]
IO0
N7[19]
IO0
N8[19]
IO0
N9
IO/VREF0
N10
IO0
N11
GCLK0
N12
GND
N13
GND
N14
GND
N15
GND
N16
GCLK1
N17
IO5
N18
IO/VREF5
N19[19]
IO5
N20[19]
IO5
N21[19]
IO5
N22
IO5
N23
IO5
N24
GND
N25
GND
N26
GND
P1
GND
P2
GND
P3
GND
P4
IO1
P5
IO1
P6
IO1
P7
IO1
P8[19]
IO1
P9[19]
IO1
P10[19]
IO1
P11
IO1
P12
GND
P13
GND
P14
GND
P15
GND
P16
IO4
P17[19]
IO4
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
CY39165
CY39200
P18[19]
IO4
P19[19]
IO4
P20
IO5
P21
IO5
P22
IO4
P23
IO4
P24
GND
P25
GND
P26
GND
R1
NC
R2
NC
R3
NC
IO1
R4
IO1
R5
IO1
R6
IO1
R7
VCCPRG
R8
VCCIO1
R9
IO/VREF1
R10
IO1
R11
IO1
R12
GND
R13
GND
R14
GND
R15
GND
R16
IO4
R17
IO4
R18
IO/VREF4
R19
VCCIO4
R20
VCCPRG
R21
IO4
R22
IO4
R23
IO4
R24
NC
IO4
R25
NC
R26
NC
T1
NC
T2
NC
T3
NC
IO/VREF1
T4
NC
VCCIO1
T5
IO/VREF1
T6
IO1
T7
VCC
T8
VCCIO1
T9
IO/VREF1
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
CY39165
CY39200
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CY3950V484-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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