參數(shù)資料
型號(hào): CY3950V484-125BBC
廠商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁(yè)數(shù): 77/86頁(yè)
文件大?。?/td> 1212K
代理商: CY3950V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 79 of 86
F6
GND
F7
IO7
F8
IO7
F9
IO7
F10
IO7
F11
IO/VREF7
F12
IO/VREF7
F13
IO6/Lock
F14
IO6
F15
IO/VREF6
F16
IO/VREF6
F17
IO6
F18
IO6
F19
IO6
F20
IO6
F21
GND
F22
NC
IO5
F23
VCCIO5
F24
NC
IO/VREF5
F25
NC
F26
NC
G1
NC
G2
NC
G3
NC
IO0
G4
NC
IO0
G5
NC
IO0
G6
IO0
G7
GND
G8
IO7
G9
IO7
G10
IO7
G11
VCCIO7
G12
VCC
G13
IO/VREF7
G14
IO/VREF6
G15
VCCPLL
G16
VCCIO6
G17
IO6
IO6[20]
IO6
G18
IO6
G19
IO6
G20
GND
G21
TDO
G22
NC
IO5
G23
NC
IO5
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
CY39165
CY39200
G24
NC
IO5
G25
NC
G26
NC
H1
NC
H2
NC
H3
NC
IO0
H4
IO0
H5
IO0
H6
IO0
H7
IO0
H8
GND
H9
IO7
H10
IO7
H11
VCCIO7
H12
VCCIO7
H13[19]
IO7
H14[19]
IO6
H15
VCCIO6
H16
VCCIO6
H17
IO6
H18
IO6
IO6[20]
IO6
H19
GND
H20
TDI
H21
IO5
H22
IO5
H23
IO5
H24
NC
IO5
H25
NC
H26
NC
J1
NC
J2
NC
J3
NC
IO0
J4
IO0
J5
IO0
J6
IO0
J7
IO0
J8
IO0
J9
GND
J10
IO7
J11
IO/VREF7
J12
IO7
J13[19]
IO7
J14[19]
IO6
J15
IO6
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
CY39165
CY39200
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CY3950V484-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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CY3950V484-125MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3950V484-125MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities