- 您現在的位置：買賣IC網 > PDF目錄379008 > CY2CC1910SIT (CYPRESS SEMICONDUCTOR CORP) 1:10 Clock Fanout Buffer with Output Enable PDF資料下載
參數資料
| 型號： | CY2CC1910SIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1:10 Clock Fanout Buffer with Output Enable |
| 中文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 129K |
| 代理商： | CY2CC1910SIT |
1:10 Clock Fanout Buffer with Output Enable
COMLINK SERIES
CY2CC1910
Cypress Semiconductor Corporation
Document #: 38-07347 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 26, 2002
408-943-2600
Features
Low-voltage operation
Full-range support:
—
3.3V
—
2.5V
—
1.8V
1:10 fanout
Drives either a 50-Ohm or 75-Ohm load
Over voltage tolerant input hot swappable
Low-input capacitance
Low-output skew
Low-propagation delay
Typical (tpd < 4 ns)
High-speed operation:
—
100 MHz@1.8V
—
200 MHz@2.5V/3.3V
Industrial versions available
Available packages include: SOIC, SSOP
Block Diagram
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
Cypress employs unique AVCMOS-type outputs VOI
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors; they also reduce noise overall.
Pin Description
Pin Number
Pin Name
Pin Description
Power
Power
LVTTL/LVCMOS
LVTTL/LVCMOS
AVCMOS
1, 7, 8, 12, 13, 17, 20, 24
3,10,15,22
5
6
2, 4, 9, 11, 14, 16, 18, 19, 21, 23 Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 Output
G
ND
V
DD
OE#
IN
Ground
Power Supply
Output Enable
Input
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24 pin SOIC/SSOP
C
GND
Q1
VDD
Q2
GND
Q3
Q4
GND
Q5
VDD
Q6
GND
GND
Q10
VDD
Q9
OE#
IN
GND
GND
Q8
VDD
Q7
GND
16
11
14
18
23
19
21
9
4
2
6
OUTPUT
(AVCMOS)
OE#
5
IN
Q5
Q7
Q6
Q4
Q1
Q3
Q2
Q8
Q9
Q10
GND
VDD
1,12,13
17,24
3,10
15,22
AVCMOS
AVCMOS
Pin Configuration
相關PDF資料 |
PDF描述 |
|---|---|
| CY2DP814SC | 1:4 Clock Fanout Buffer |
| CY2DP814ZC | DB37 INTERFACE DATA CBL DB37 Male - DB37 Female |
| CY2DP814ZCT | DB37 INTERFACE DATA CBL DB37 Male - DB37 Female |
| CY2DP814 | 1:4 Clock Fanout Buffer |
| CY2DP814SCT | 1:4 Clock Fanout Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY2CC810 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:10 Clock Fanout Buffer |
| CY2CC810_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:10 Clock Fanout Buffer |
| CY2CC8100I | 制造商:Cypress Semiconductor 功能描述: |
| CY2CC8100XC-1 | 制造商:Cypress Semiconductor 功能描述: |
| CY2CC8100XI | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。