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參數(shù)資料
| 型號： | CY2DP814ZCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | DB37 INTERFACE DATA CBL DB37 Male - DB37 Female |
| 中文描述： | 2DP SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, MO-153, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 120K |
| 代理商： | CY2DP814ZCT |
1:4 Clock Fanout Buffer
ComLink Series
CY2DP814
Cypress Semiconductor Corporation
Document #: 38-07060 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 15, 2002
408-943-2600
Features
Low voltage operation
V
DD
= 3.3V
1:4 fanout
Single-input configurable for LVDS, LVPECL, or LVTTL
Four differential pairs of LVPECL outputs
Drives 50-ohm load
Low input capacitance
Low output skew
Low propagation delay
—
Typical (tpd < 4 ns)
Industrial versions available
Available packages include TSSOP, SOIC
Description
The Cypress CY2 series of network circuits are produced
using advanced 0.35-micron CMOS technology, achieving the
industry
’
s fastest logic.
The Cypress CY2DP814 fanout buffer features a single LVDS-
or a single LVPECL-compatible input and four LVPECL output
pairs.
Designed for data communications clock management appli-
cations, the fanout from a single input reduces loading on the
input clock.
The CY2DP814 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVDS-based clock signals. The Cypress CY2DP814 has
configurable input between logic families. The input can be
selectable for an LVPECL/LVTTL or LVDS signal, while the
output drivers support LVPECL capable of driving 50-ohm
lines.
Block Diagram
Pin Configuration
OUTPUT
LVPECL
IN+ 6
IN- 7
16 Q1A
15 Q1B
14 Q2A
13 Q2B
10 Q4A
9 Q4B
12 Q3A
11 Q3B
LVDS /
LVPECL /
LVTTL
CONFIG 2
EN1 1
EN2 8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
16 pin TSSOP / SOIC
EN1
CONFIG
VDD
VDD
GND
IN+
IN-
EN2
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2DP814 | 1:4 Clock Fanout Buffer |
| CY2DP814SCT | 1:4 Clock Fanout Buffer |
| CY2DP814SI | 1:4 Clock Fanout Buffer |
| CY2DP814SIT | 1:4 Clock Fanout Buffer |
| CY2DP814ZI | 1:4 Clock Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2DP814ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:4 Clock Fanout Buffer |
| CY2DP814ZIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:4 Clock Fanout Buffer |
| CY2DP814ZXC | 功能描述:時鐘緩沖器 3.3V 400MHz LVDS Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2DP814ZXCT | 功能描述:時鐘緩沖器 3.3V 450MHz COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2DP814ZXI | 功能描述:時鐘緩沖器 3.3V 450MHz IND RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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