參數(shù)資料
型號(hào): CY29948
廠商: Cypress Semiconductor Corp.
英文描述: 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
中文描述: 2.5V或3.3V,200兆赫,1:12時(shí)鐘分配緩沖區(qū)
文件頁(yè)數(shù): 3/7頁(yè)
文件大?。?/td> 108K
代理商: CY29948
CY29948
Document #: 38-07288 Rev. *B
Page 3 of 7
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
:............. V
SS
0.3V
Maximum Input Voltage Relative to V
DD
:.............V
DD
+ 0.3V
Storage Temperature: ................................
65
°
C to + 150
°
C
Operating Temperature:................................
40
°
C to +85
°
C
Maximum ESD protection...............................................2 kV
Maximum Power Supply:................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
or V
DD
).
Notes:
2.
3.
4.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Inputs have pull-up/pull-down resistors that effect input current.
The V
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the
High
input is within the V
CMR
range and the input lies within the V
specification.
Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
5.
DC Parameters:
V
DD
= V
DDC
= 3.3V ±10% or 2.5V ±5%, Over the specified temperature range
Parameter
V
IL
Description
Conditions
Min.
1.49
1.10
V
SS
2.135
1.75
2.0
Typ.
Max.
1.825
1.45
0.8
2.42
2.0
V
DD
100
100
1000
Unit
V
Input Low Voltage
V
DD
= 3.3V, PECL_CLK single ended
V
DD
= 2.5V, PECL_CLK single ended
All other inputs
V
DD
= 3.3V, PECL_CLK single ended
V
DD
= 2.5V, PECL_CLK single ended
All other inputs
V
IH
Input High Voltage
V
I
IL
I
IH
V
PP
Input Low Current
[3]
Input High Current
[3]
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
[4]
PECL_CLK
μA
300
mV
V
CMR
V
DD
= 3.3V
V
DD
= 2.5V
I
OL
= 20 mA
I
OH
=
20 mA, V
DD
= 3.3V
I
OH
=
20 mA, V
DD
= 2.5V
V
DD
2.0
V
DD
1.2
V
DD
0.6
V
DD
0.6
0.4
V
V
OL
V
OH
Output Low Voltage
[5]
Output High Voltage
[5]
V
V
2.5
1.8
I
DDQ
Quiescent Supply
Current
Dynamic Supply
Current
5
7
mA
I
DD
V
DD
= 3.3V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 3.3V, Outputs @ 160 MHz,
CL = 30 pF
V
DD
= 2.5V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 2.5V, Outputs @ 160 MHz,
CL = 30 pF
V
DD
= 3.3V
V
DD
= 2.5V
180
mA
270
125
190
Zout
Output Impedance
12
14
15
18
4
18
22
C
in
Input Capacitance
pF
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