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參數(shù)資料
| 型號： | CY29972 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V, 125-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 3.3伏，125 MHz的多輸出零延遲緩沖器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 70K |
| 代理商： | CY29972 |
3.3V, 125-MHz Multi-Output Zero Delay Buffer
CY29972
Cypress Semiconductor Corporation
Document #: 38-07290 Rev. *A
3901 North First Street
San Jose
CA 95134
408-943-2600
December 22, 2002
2
Features
Output frequency up to 125 MHz
12 Clock outputs: frequency configurable
350 ps max. output-to-output skew
Configurable output disable
Two reference clock inputs for dynamic toggling
Oscillator or crystal reference input
Spread-spectrum-compatible
Glitch-free output clocks transitioning
3.3V power supply
Pin-compatible with MPC972
Industrial temperature range: –40°C to +85°C
52-pin TQFP package
Table 1. Frequency Table
[1]
VC0_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note:
1.
x = the reference input frequency, 200 MHz < F
VCO
< 480 MHz.
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
VC0
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
Block Diagram
Pin Configuration
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
XIN
XOUT
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
VDD
F
S
V
Q
V
Q
S
S
Q
V
Q
V
I
S
S
S
S
Q
V
Q
V
Q
V
Q
V
V
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29972
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY29972_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 125-MHz Multi-Output Zero Delay Buffer |
| CY29972_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V, 125-MHz Multi-Output Zero Delay Buffer Output frequency up to 125 MHz |
| CY29972_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V, 125-MHz Multi-Output Zero Delay Buffer |
| CY29972AI | 功能描述:IC CLK ZDB 12OUT 125MHZ 52TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| CY29972AIT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 200MHz to 480MHz 52-Pin TQFP T/R |
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