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參數(shù)資料
| 型號： | CY29972 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V, 125-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 3.3伏，125 MHz的多輸出零延遲緩沖器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 70K |
| 代理商： | CY29972 |
CY29972
Document #: 38-07290 Rev. *A
Page 6 of 8
Maximum Ratings
[5]
Maximum input voltage relative to V
SS
:.............. V
SS
–
0.3V
Maximum input voltage relative to V
DD
:...............V
DD
+ 0.3V
Storage temperature:.............................
–
65
×
C to +150
×
C
Operating temperature:............................
–
40
×
C to +85
×
C
Maximum ESD protection................................................2kV
Maximum power supply: .................................................5.5V
Maximum input current: .............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD .
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= 2.9V to 3.6V, V
DDC
= 3.3V ±10%, T
A
=
–
40
°
C to +85
°
C
Parameter
Description
V
IL
Input Low Voltage
V
IH
Input High Voltage
I
IL
I
IH
Input High Current
V
OL
V
OH
I
DDQ
Quiescent Supply Current
I
DDA
PLL Supply Current
Test Conditions
Min.
V
SS
2.0
Typ.
–
–
–
Max.
0.8
V
DD
–
120
10
0.5
Unit
V
V
μA
μA
V
V
mA
mA
Input Low Current
[6]
Output Low Voltage
[7]
Output High Voltage
[7]
IOL = 20mA
IOH =
–
20mA
2.4
–
10
15
225
125
4
15
20
V
DD
only
QA and QB @ 60 MHz, QC @ 120 MHz, CL = 30 pF
QA and QB @ 25 MHz, QC @ 50 MHz, CL = 30pF
I
DD
Dynamic Supply Current
mA
C
IN
Notes:
5.
6.
7.
AC Parameters
V
DD
= 2.9V to 3.6V, V
DDC
= 3.3V ±10%, T
A
=
–
40
°
C to +85
°
C
[8]
Parameter
Description
Tr / Tf
TCLK Input Rise/Fall
Fref
Reference Input Frequency
Fxtal
Crystal Oscillator Frequency
FrefDC
Reference Input Duty Cycle
Fvco
PLL VCO Lock Range
Tlock
Maximum PLL Lock Time
Tr / Tf
Output Clocks Rise / Fall Time
[10]
Input Pin Capacitance
–
-
pF
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Inputs have pull-up/pull-down resistors that effect input current.
Driving series or parallel terminated 50
(or 50
to V
DD/2
) transmission lines.
Conditions
Min
Typ
Max
3.0
Note 9
25
75
480
10
1.2
125
120
80
60
Unit
ns
MHz
MHz
%
MHz
ms
ns
Note 9
10
25
200
see
Table 3
0.8V to 2.0V
Q (
÷
2)
Q (
÷
4)
Q (
÷
6)
Q (
÷
8)
0.15
-
Fout
Maximum Output Frequency
MHz
FoutDC
tpZL, tpZH
tpLZ, tpHZ
TCCJ
TSKEW
Output Duty Cycle
[10]
Output Enable Time
[10]
(all outputs)
Output Disable Time
[10]
(all outputs)
Cycle to Cycle Jitter
[10]
(peak to peak)
Any Output to Any Output Skew
[10,11]
TCYCLE/2
–
750
2
2
TCYCLE/2 + 750
10
8
ps
ns
ns
ps
ps
± 100
250
130
70
350
530
470
Tpd
Propagation Delay
[11,12]
T
CLK0
T
CLK1
QFB = (
÷
8)
–
270
–
330
ps
Notes:
8.
9.
10. Maximum and minimum input reference is limited by VC0 lock range.
11.
50W transmission line terminated into V
.
12. Tpd is specified for a 50 MHz input reference. Tpd does not include jitter.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
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