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參數(shù)資料
| 型號： | CY29948 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer |
| 中文描述： | 2.5V或3.3V，200兆赫，1:12時鐘分配緩沖區(qū) |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 108K |
| 代理商： | CY29948 |
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
CY29948
Cypress Semiconductor Corporation
Document #: 38-07288 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 22, 2002
408-943-2600
48
Features
2.5V or 3.3V operation
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS-/LVTTL-compatible inputs
12 clock outputs: drive up to 24 clock lines
Synchronous Output Enable
Output three-state control
250 ps max. output-to-output skew
Pin compatible with MPC948, MPC948L, MPC9448
Available in Commercial and Industrial temp. range
32-pin TQFP package
Description
The CY29948 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The 12 outputs are LVCMOS or LVT-
TL compatible and can drive 50
series or parallel terminated
transmission lines. For series terminated transmission lines,
each output can drive one or two traces giving the device an
effective fanout of 1:24. The outputs can also be three-stated
via the three-state input TS#. Low output-to-output skews
make the CY29948 an ideal clock distribution buffer for nested
clock trees in the most demanding of synchronous systems.
The CY29948 also provides a synchronous output enable in-
put for enabling or disabling the output clocks. Since this input
is internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
SYNC_OE
TS#
VDD
VDDC
12
Q0-Q11
CY29948
V
Q
V
Q
V
Q
V
Q
Q
V
Q
V
Q
V
Q
V
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
相關PDF資料 |
PDF描述 |
|---|---|
| CY29948AC | 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer |
| CY29948ACT | 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer |
| CY29948AI | 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer |
| CY29948AIT | 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer |
| CY29972 | 3.3V, 125-MHz Multi-Output Zero Delay Buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY29948_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer |
| CY29948_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer LVCMOS-/LVTTL-compatible inputs |
| CY29948_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer |
| CY29948AC | 功能描述:IC CLOCK BUFFER MUX 2:12 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:- 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| CY29948ACT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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