參數(shù)資料
型號(hào)： CY28548ZXCT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 29/30頁(yè)
文件大小： 0K
描述： IC CLK CK505 960M/965M 64TSSOP
標(biāo)準(zhǔn)包裝： 2,000
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 時(shí)鐘
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 3:22
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TFSOP （0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 64-TSSOP
包裝： 帶卷 (TR)
CY28548
........................Document #: 001-08400 Rev ** Page 8 of 30
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
.
57
FSB / TEST_MODE
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode:
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58
VSS_REF
GND
Ground for outputs.
59
Xout
O, SE 14.318 MHz Crystal output.
60
Xin
I
14.318 MHz Crystal input.
61
VDD_REF
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power down.
62
REF0 / FSC / TEST_SEL
I/O
Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency selection /
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifica-
tions.
63
SDATA
I/O
SMBus-compatible SDATA.
64
SCLK
I
SMBus-compatible SCLOCK.
TSSOP Pin Definitions (continued)
Pin No.
Name
Type
Description
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
FSB
FSA
CPU
SRC
PCIF/PCI
27MHz
REF
DOT96
USB
0
266 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
133 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
166 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
0
333 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
0
1
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
0
400 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
Reserved
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
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