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參數(shù)資料
| 型號： | CY28347ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP-56 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 188K |
| 代理商： | CY28347ZC |
CY28347
Document #: 38-07352 Rev. *C
Page 6 of 22
4
1
17
PCI5
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
3
1
15
PCI4
2
1
14
PCI3
1
1
12
PCI2
0
1
11
PCI1
Byte 3: AGP/Peripheral Clocks Register
Bit
7
@Pup
0
Pin#
21
Name
24_48M
Description
“
0
”
= pin 21 output is 24 MHz. Writing a
“
1
”
into this register
asynchronously changes the frequency at pin 21 to 48 MHz.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
Programming these bits allow shifting skew of the AGP(0:2)
signals relative to their default value. See
Table 7
.
6
1
20
48MHz
5
1
21
24_48M
4
3
2
1
0
0
1
1
6,7,8
6,7,8
DASAG1
DASAG0
Reserved, set = 1.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
7
AGP1
0
1
6
AGP0
Byte 4: Peripheral Clocks Register
Bit
7
@Pup
1
Pin#
20
Name
48M
Description
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
Programming these bits allow modifying the frequency ratio of
the AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See
Table 8
.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state. (K7 Mode only.)
1 = strength x 1. 0 = strength x 2
1 = strength x 1. 0 = strength x 2 (K7 Mode only)
6
1
21
24_48M
5
4
0
0
6,7,8
6,7,8
DARAG1
DARAG0
3
1
1
REF0
2
1
56
REF1
1
0
1
1
1
REF0
REF1
56
Byte 2: PCI Clock Register
(continued)
Bit
@Pup
Pin#
Name
Description
Table 7. Dial-a-Skew
AGP(0:2)
DASAG (1:0)
00
01
10
11
AGP(0:2) Skew Shift
Default
–
280 ps
+280 ps
+480 ps
相關PDF資料 |
PDF描述 |
|---|---|
| CY28347ZCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28349B | FTG for Intel Pentium 4 CPU and Chipsets |
| CY28349BOC | FTG for Intel Pentium 4 CPU and Chipsets |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28347ZCT | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Tape and Reel |
| CY28349 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
| CY28349B | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
| CY28349B_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
| CY28349BOC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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