參數(shù)資料
型號(hào)： CY28347ZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
中文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6 X 14 MM, TSSOP-56
文件頁(yè)數(shù)： 2/22頁(yè)
文件大?。?/td> 188K
代理商： CY28347ZC
CY28347
Document #: 38-07352 Rev. *C
Page 2 of 22
Pin Description
[2]
Pin
Name
PWR
I/O
I
O
Description
3
4
XIN
XOUT
Oscillator Buffer Input
. Connect to a crystal or to an external clock.
Oscillator Buffer Output
. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
Power-on Bidirectional Input/Output
. At power-up, FS0 is the input. When the
power supply voltage crosses the input threshold voltage, FS0 state is latched and
this pin becomes REF0, buffered copy of signal applied at XIN. (1
–
2 x strength,
selectable by SMBus. Default value is 1 x strength.)
If SELP4_K7# = 1, with a P4 processor setup as CPU(T:C)
. At power-up,
VTT_PWRGD# is an input. When this input is sampled LOW, the FS (3:0) and
MULTSEL are latched and all output clocks are enabled. After the first transition to
a LOW on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the
device thereafter. When the VTT_PWRGD# feature is not used, please connect this
signal to ground through a 10K
resistor.
If SELP4_K7# = 0, with an Athlon (K7) processor as CPUOD_(T:C)
.
VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes
REF1 and is a buffered copy of the signal applied at XIN.
These pins are configured for DDR clock outputs
. They are
“
True
”
copies of
signal applied at Pin45, BUF_IN.
These pins are configured for DDR clock outputs
. They are
“
Complementary
”
copies of signal applied at Pin45, BUF_IN.
Power-on Bidirectional Input/Output
. At power-up, SELP4_K7# is the input.
When the power supply voltage crosses the input threshold voltage, SELP4_K7#
state is latched and this pin becomes AGP1 clock output. SELP4_K7# = 1 selects
P4 mode. SELP4_K7# = 0 selects K7 mode.
Power-on Bidirectional Input/Output
. At power-up, MULTSEL is the input. When
the power supply voltage crosses the input threshold voltage, MULTSEL state is
latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x
IREFMULTSEL = 1, Ioh is 6 x IREF
3.3V True CPU Clock Outputs
. This pin is programmable through strapping pin7,
SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7# = 0, this pin is configured as the CPUOD_T Open Drain Clock Output.
See
Table 1.
3.3V Complementary CPU Clock Outputs
. This pin is programmable through
strapping pin7, SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUC
Clock Output. If SELP4_K7# = 0, this pin is configured as the CPUOD_C Open
Drain Clock Output. See
Table 1.
PCI Clock Outputs
. Are synchronous to CPU clocks. See
Table 1.
2.5V CPU Clock Outputs for Chipset
. See
Table 1
.
If pin 6 is pulled down at power on reset, then this pin becomes CPU_STP#. When
CPU_STP# is asserted LOW, then both of the CPU signals stop at the next HIGH
to LOW transition or stays LOW if it already is LOW. This does not stop the CPUCS
signals.
Power-on Bidirectional Input/Output
. At power-up, FS1 is the input. When the
power supply voltage crosses the input threshold voltage, FS1 state is latched and
this pin becomes PCI_F clock output.
Power-on Bidirectional Input/Output
. At power-up, FS3 is the input. When the
power supply voltage crosses the input threshold voltage, FS3 state is latched and
this pin becomes 48M, a USB clock output.
PCI Clock Output
.
Power-on Bidirectional Input/Output.
At power-up, FS2 is the input. When the
power supply voltage crosses the input threshold voltage, FS2 state is latched and
this pin becomes 24_48M, a SIO programmable clock output.
VDD
1
FS0/REF0
VDD
I/O
PU
56
VTTPWRGD#
VDDR
I
REF1
VDDR
O
44,42,38,
36,32,30
43,41,37
35,31,29
7
DDRT(0:5)
VDDD
O
DDRC(0:5)
VDDD
O
SELP4_K7#/
AGP1
VDDAGP
I/O
PU
12
MULTSEL/PCI2 VDDPCI
I/O
PU
53
CPUT/CPUOD_T
VDDC
O
52
CPUC/CPUOD_C
VDDC
O
14,15,17
48,49
18
PCI (3:5)
CPUCS_T/C
CPU_STP#
VDDPCI
VDDI
VDDPCI
O
O
I
PU
10
FS1/PCI_F
VDDPCI
I/O
PD
20
FS3/48M
VDD48M
I/O
PD
11
21
PCI1
FS2/24_48M
VDDPCI
VDD48M
O
I/O
PD
Note:
2.
PU = internal pull-up. PD = internal pull-down. Typically = 250 k
(range 200 k
to 500 k
).
相關(guān)PDF資料
PDF描述
CY28347ZCT Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28347OC Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28347OCT Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28349B FTG for Intel Pentium 4 CPU and Chipsets
CY28349BOC FTG for Intel Pentium 4 CPU and Chipsets
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28347ZCT 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Tape and Reel
CY28349 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349B 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349B_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349BOC 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*