參數(shù)資料
型號: CY28347ZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
中文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6 X 14 MM, TSSOP-56
文件頁數(shù): 11/22頁
文件大?。?/td> 188K
代理商: CY28347ZC
CY28347
Document #: 38-07352 Rev. *C
Page 11 of 22
Tr / Tf
CPUCS_T/C Rise and
Fall Times
Differential Voltage AC
0.4
1.6
0.4
1.6
0.4
1.6
0.4
1.6
ns 5,10,21
VD
0.4
Vp+
0.6V
0.5*VD
DI+0.2
0.4
Vp+
0.6V
0.5*VD
DI+0.2
0.4
Vp+
0.6V
0.5*VD
DI+0.2
0.4
Vp+
0.6V
0.5*VD
DI+0.2
V 24
VX
Differential Crossover
Voltage
0.5*VD
DI
0.2
0.5*VD
DI
0.2
0.5*VD
DI
0.2
0.5*VD
DI
0.2
V 14
AGP
TDC
TPeriod
THIGH
TLOW
Tr/Tf
AGP(0:2) Duty Cycle
AGP(0:2) Period
AGP(0:2) HIGH Time
AGP(0:2) LOW Time
AGP(0:2) Rise and Fall
Times
Any AGP to Any AGP
Clock Skew
AGP(0:2) Cycle-to-Cycle
Jitter
45
15
5.25
5.05
0.4
55
16
45
15
5.25
5.05
0.4
55
16
45
15
5.25
5.05
0.4
55
16
45
15
5.25
5.05
0.4
55
16
% 5,6,10
ns 5,6,10
ns 10,25
ns 10,18
ns 10,21
1.6
1.6
1.6
1.6
TSKEW
250
250
250
250
ps 10,11,12
TCCJ
500
500
500
500
ps 6,10,11,12
PCI
TDC
TPeriod
THIGH
TLOW
Tr/Tf
PCI(_F,1:6) Duty Cycle
PCI(_F,1:6) Period
PCI(_F,1:6) HIGH Time
PCI(_F,1:6) LOW Time
PCI(_F,1:6) Rise and Fall
Times
Any PCI to Any PCI Clock
Skew
PCI(_F,1:6)
Cycle-to-Cycle Jitter
45
30.0
12.0
12.0
0.5
55
45
30.0
12.0
12.0
0.5
55
45
30.0
12.0
12.0
0.5
55
45
30.0
12.0
12.0
0.5
55
% 5,6,10
ns 5,6,10
ns 10,25
ns 10,18
ns 10,21
2.0
2.0
2.0
2.0
TSKEW
500
500
500
500
ps 10,11,12
TCCJ
500
500
500
500
ps 10,6,11,12
48 MHz
TDC
TPeriod
Tr/Tf
48-MHz Duty Cycle
48-MHz Period
48-MHz Rise and Fall
Times
48-MHz Cycle-to-Cycle
Jitter
45
55
45
55
45
55
45
55
% 5,6,10
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 5,6,10
1.0
4.0
1.0
4.0
1.0
4.0
1.0
4.0
ns 10,21
TCCJ
500
500
500
500
ps 10,6,11,12
24 MHz
TDC
TPeriod
Tr / Tf
24-MHz Duty Cycle
24-MHz Period
24-MHz Rise and Fall
Times
24-MHz Cycle-to-Cycle
Jitter
45
55
45
55
45
55
45
55
% 5,6,10
ns 5,6,10
ns 10,21
41.660 41.667 41.660 41.667 41.660 41.667 41.660 41.667
1.0
4.0
1.0
4.0
1.0
4.0
1.0
4.0
TCCJ
500
500
500
500
ps 6,10,11,12
Notes:
24. Measured at VX between the falling edge and the following rising edge of the signal.
25. Probes are placed on the pins, and measurements are acquired at 0.4V.
AC Parameters
(continued)
Parameter
Description
66 MHz
Min.
100 MHz
Min.
133 MHz
Min.
200 MHz
Min.
Unit
Notes
Max.
Max.
Max.
Max.
相關PDF資料
PDF描述
CY28347ZCT Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28347OC Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28347OCT Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
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