參數(shù)資料
型號： CY28347ZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
中文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6 X 14 MM, TSSOP-56
文件頁數(shù)： 10/22頁
文件大小： 188K
代理商： CY28347ZC
CY28347
Document #: 38-07352 Rev. *C
Page 10 of 22
P4 Mode CPU at 0.7V
TDC
TPeriod
Tr/Tf
CPUT/C Duty Cycle
CPUT/C Period
CPUT/C Rise and Fall
Times
Rise/Fall Matching
45
55
15.3
700
45
9.85
175
55
10.2
700
45
7.35
175
55
7.65
700
45
4.85
175
55
5.1
700
% 5,6,10,14,15
ns 5,6,10,14,15
ps 15,16
14.85
175
20%
125
100
20%
125
100
20%
125
100
20%
125
100
16,17
Delta Tr/Tf Rise/Fall Time Variation
TSKEW
CPUT/C to CPUCS_T/C
Clock Skew
TCCJ
CPUT/C Cycle-to-Cycle
Jitter
Vcross
Crossing Point Voltage
P4 Mode CPU at 1.0V
TDC
CPUT/C Duty Cycle
TPeriod
CPUT/C Period
Differ-
ential Tr/Tf
Times
Delta Tr/Tf Rise/Fall Time Variation
TSKEW
CPUT/C to CPUCS_T/C
Clock Skew
TCCJ
CPUT/C Cycle-to-Cycle
Jitter
Vcross
Crossing Point Voltage
SE-
DeltaSlew
Rise/Fall Waveform
Symmetry
K7 Mode
TDC
CPUOD_T/C Duty Cycle
TPeriod
CPUOD_T/C Period
TLOW
CPUOD_T/C LOW Time
Tf
CPUOD_T/C Fall Time
TCCJ
CPUOD_T/C
Cycle-to-Cycle Jitter
VD
Differential Voltage AC
VX
Differential Crossover
Voltage
Chipset
TDC
CPUCS_T/C Duty Cycle
TPeriod
CPUCS_T/C Period
ps 10,15,16,18
ps 10,11,12,14,1
5
ps 6,10,11,12,14,
15
mV 15.
150
150
150
150
280
430
280
430
280
430
280
430
45
55
15.3
467
45
9.85
175
55
10.2
467
45
7.35
175
55
7.65
467
45
4.85
175
55
5.1
467
% 5,10,6,14
nS 5,10,6,14
ps 10,11,19
14.85
175
CPUT/C Rise and Fall
125
100
125
100
125
100
125
100
ps 10,18
ps 10,11,12,14
150
150
150
150
ps 10,11,12,14
510
760
325
510
760
325
510
760
325
510
760
325
mV 19
ps 20
Absolute Single-ended
45
55
15.3
45
9.85
2.8
0.4
55
10.2
45
7.35
1.67
0.4
55
7.65
45
4.85
2.8
0.4
55
5.1
% 5,6,10
ns 5,6,10
ns 5,6,10
ns 5,10,21
ps 6,10
14.85
2.8
0.4
1.6
±250
1.6
±250
1.6
±250
1.6
±250
.4
500
Vp+.6V
1100
.4
Vp+.6V
1100
.4
Vp+.6V
1100
.4
500
Vp+.6V
1100
V 22
mV 23
500
500
45
15
55
15.5
45
10.0
55
10.5
45
7.35
55
7.65
45
4.85
55
5.1
% 5,10,6
ns 5,10,6
Notes:
14. Measured at VX between the rising edge and the following falling edge of the signal.
15. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).
16. See figure 6 for 0.7V loading specification.
17. Measurement taken from differential waveform, from -0.35V to +0.35V.
18. The time specified is measured from when all VDD
’
s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within
specifications.
19. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), you should
add the same length transmission line to the other signal of the pair (e.g., AGP).
20. Measured in absolute voltage, i.e., single-ended measurement.
21. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.
22. Measured at VX, or where subtraction of CLK
–
CLK# crosses 0 volts.
23. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary
DDRC (and CPUCS_C) one.
AC Parameters
(continued)
Parameter
Description
66 MHz
Min.
100 MHz
Min.
133 MHz
Min.
200 MHz
Min.
Unit
Notes
Max.
Max.
Max.
Max.
相關(guān)PDF資料
PDF描述
CY28347ZCT Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28347OC Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems
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CY28349B FTG for Intel Pentium 4 CPU and Chipsets
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28347ZCT 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Tape and Reel
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CY28349B 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349B_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349BOC 制造商:Rochester Electronics LLC 功能描述:- Bulk
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