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參數(shù)資料
| 型號： | CXK77910ATM |
| 廠商： | Sony Corporation |
| 英文描述： | 131,072-Word by 9-Bit High-Speed Synchronous Static RAM(131072字 × 9位高速同步靜態(tài)RAM) |
| 中文描述： | 131,072由9位字高速同步靜態(tài)存儲器（131072字× 9位高速同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 187K |
| 代理商： | CXK77910ATM |
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E93831C52–ST
CXK77910ATM/AYM
-10/12
131,072-word by 9-bit High-Speed Synchronous Static RAM
Description
The CXK77910ATM/AYM are high-speed CMOS
synchronous static RAMs with common I/O pins,
organized
as
131,072-word-by-9-bit.
synchronous SRAMs integrate input registers, high
speed SRAM and output registers onto a single
monolithic IC. All input signals are latched at the positive
edge of an external clock (CLK). The RAM data from the
previous cycle is presented at the positive edge of the
subsequent clock cycle. Write operation is initiated by
the positive edge of CLK and is internally self-timed.
This feature eliminates complex off-chip write pulse
generation and provides increased flexibility for
incoming signals. 100MHz operation is obtained from a
single 5V power supply.
These
Function
There are three possible user transactions with the
STRAM — read operation, write operation and deselect
operation.
The read operation requires WE = "HIGH" and OE =
CE = "LOW" on the positive edge of CLK.
The memory location pointed to by the contents of the
Address registers is read internally and the contents of
the location are captured in the Data-out registers on the
next positive edge of CLK. The state of Data-out will
reflect the contents of the Data-out registers.
The write operation requires CE = WE = "LOW" on
the positive edge of CLK. The memory location pointed
to by the contents of the Address registers is written with
the contents of the Data-in registers. The write operation
is entirely self-timed, eliminating critical timing edges.
The deselect cycle requires CE = "HIGH" or OE = WE
= "HIGH" on the positive edge of CLK. Write operation
and internal read operation are disabled during the clock
cycle. The data outputs are forced to a high impedance
state during the next clock cycle. During the deselect
cycle by CE = "HIGH", STRAM turns to power down
mode.
Structure
Silicon gate CMOS IC
Features
Fast cycle time:
CXK77910ATM/AYM-10
CXK77910ATM/AYM-12
Fast clock to data valid
CXK77910ATM/AYM-10
CXK77910ATM/AYM-12
High speed, low power consumption
Single +5V power supply: 5V ± 5%
Separate output power supply: 3.15V to 5.25V
Inputs and outputs are TTL compatible (3.3V I/O
compatible)
Common data input and output
All inputs and outputs are registered on a single clock
edge
Self-timed write cycle
Package line-up: 400mil 44 pin TSOP II with 0.8mm
pitch
(Cycle) (Frequency)
10.0ns
12.5ns
100MHz
80MHz
5.5ns
6.5ns
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication
or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
CXK77910ATM
44-pin TSOP(II)(Plastic)
CXK77910AYM
44-pin TSOP(II)(Plastic)
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| CXK77B3641AGB | 4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位)) |
| CXK77B1841GB | 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位)) |
| CXK77B3611AGB- | High Speed Bi-CMOS Synchronous Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77910ATM-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
| CXK77910AYM-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
| CXK77920TM-11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
| CXK77920TM-12 | 制造商:Sony Batteries 功能描述: 制造商:Sony Batteries 功能描述:256K X 9 STANDARD SRAM, 6.5 ns, PDSO44 |
| CXK77920TM-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Synchronous SRAM |
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