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參數(shù)資料
| 型號： | CS4265-DNZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC 24BIT 104DB 32-QFN |
| 標準包裝： | 6,000 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 104 / 104 |
| 電壓 - 電源，模擬： | 3.13 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 3.13 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-QFN |
| 供應商設備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
| 配用： | 598-1001-ND - BOARD EVAL FOR CS4265 CODEC |
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DS657F3
29
CS4265
clocking change, the DAC outputs will always be in a zero-data state. If non-zero serial audio input is
present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes
to its zero-data state.
4.8
DAC Serial Data Input Multiplexer
The CS4265 contains a 2-to-1 serial data input multiplexer. This allows two separate data sources to be
input into the DAC without the use of any external multiplexing components. “Section 6.6.1 “DAC SDIN
Source (Bit 7)” on page 40” describes the control port settings necessary to control the multiplexer.
4.9
De-Emphasis Filter
The CS4265 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in Figure 13. The frequency response of the de-emphasis curve scales proportionally with
changes in sample rate, Fs. Please see Section 6.3.3 “De-Emphasis Control (Bit 1)” on page 38 for de-em-
phasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis
equalization as a means of noise reduction.
De-emphasis is only available in Single-Speed Mode.
4.10
Internal Digital Loopback
The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input
of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See “Signal
When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4265.
Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until
the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the
format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present onthe SDOUT pin
in the format selected by the ADC_DIF bit in register 04h.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 13. De-Emphasis Curve
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相關代理商/技術參數(shù) |
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| CS4267AM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS4270 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 192 kHz Stereo Audio CODEC |
| CS4270_06 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 192 kHz Stereo Audio CODEC |
| CS4270-CZZ | 功能描述:接口—CODEC Stereo Audio CODEC 105 dB 192 kHz RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS4270-CZZR | 功能描述:接口—CODEC IC 105dB 192kHz Stereo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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